tag: Mentor Graphics

Double Patterning: Sharing the Benefit and the Burden
By David Abercrombie - 01 Jun, 2011 - Comments: 0

By David Abercrombie Share and share alike! Our mothers always said it was the right thing to do, and it seems that this ideology is now coming front and center for double patterning at 20nm and below. As we continue to shrink the metal pitch from node to node, we also push the lithography k1 lower and lower, since we are currently stuck with 193nm/1.35NA scanners. When k1 dropped below 0.6,... » read more

ESL And FPGAs
By Jon McDonald - 26 May, 2011 - Comments: 0

By Jon McDonald I've been struggling to come up with a good way of answering a recent question: "Do ESL approaches provide benefits for FPGA design?" I have an initial gut answer that's somewhat unsatisfactory. Thinking through the subject I can see ways of looking at the question and getting both a “yes” and a “no,” but that's probably an indication my thinking is not yet clear enough... » read more

Blog Review: May 25
By Ed Sperling - 25 May, 2011 - Comments: 0

By Ed Sperling Cadence’s Richard Goering follows Jim Hogan’s talk about the democratization of MEMS. This market is showing big gains lately, but to really release the emergency brake will require a different design approach. Mentor’s Robin Bornoff revs up the engine and turns on the neon underbody lighting in this look at the overclocking market, shifting effortlessly from cars to PC... » read more

Experts At The Table: Power Budgeting
By Ed Sperling - 20 May, 2011 - Comments: 0

Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul van Besouw, presi... » read more

Extraction, Power And Final Silicon
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor technology scales down, manufacturing effects are coming front and center, putting constant pressure on design teams to make sure that silicon can be modeled through the extraction process while performing analysis accurately. Extraction technology is one of the basic components needed to gain an accurate measurement of power, timing and signal int... » read more

Intel’s New Machine
By Barry Pangrle - 12 May, 2011 - Comments: 0

By Barry Pangrle Power is one of those product characteristics that touches on every phase of the design and verification process all the way from the system architecture down to the fabrication process used for the actual IC implementation. In this month’s blog we take a look at process technology and in this case, it appears to be the case that the technology rich are getting richer. On... » read more

Experts At The Table: Power Budgeting
By Ed Sperling - 12 May, 2011 - Comments: 0

Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul van Besouw, presi... » read more

EDA’s Dr. Jekyll and Mr. Hyde
By Mentor Graphics Staff Writers - 10 May, 2011 - Comments: 0

By Joe Davis The need for tool Integration and the reality of competition create a Jekyll and Hyde dichotomy for the EDA industry. Customers are demanding functionality that requires tight integration between tools even when they come from competing EDA companies. We have some examples of success, but this remains a challenging area. Customers can help or sit on the sidelines, but integratio... » read more

‘What If’ In 3D
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling ‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node. When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design. ... » read more

EDA’s Big Challenge
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler It is not news to anyone that the growth rate of the EDA industry has been less than impressive, to put it politely. Traditional EDA implementation tools have hit commodity status and something’s got to change. Thankfully, there are a host of challenges coming in the form of system-level (and higher) design, not to mention what will be required for true 3D chips. ... » read more

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