tag: Mentor Graphics

The Week In Review: Design
By Jesse Allen - 23 Sep, 2016 - Comments: 0

Tools Real Intent updated its Ascent Lint product, adding 50 new customer-driven rules, improved support of VHDL and System Verilog, and a new database-driven debugger with an integrated source browser and improved schematic visualization. IP ARM launched a new real-time processor with advanced safety features for autonomous vehicles and medical and industrial robots. The processor, Co... » read more

The Pitfalls Of Auto-Stitching In Double-Patterning
By David Abercrombie - 22 Sep, 2016 - Comments: 0

Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Re-Coloring ECO Changes With Calibre Multi-Patterning
By Mentor, a Siemens Business - 21 Sep, 2016 - Comments: 0

Engineering change orders (ECOs) can wreak havoc on multi-patterning (MP) coloring (and time to market) if not dealt with quickly and efficiently. Design teams working on MP designs need a complete ECO enablement solution, before recoloring issues consume resources and destroy schedules. The Calibre Multi-Patterning tool provides smart, automated support for recoloring designs after ECO impleme... » read more

Blog Review: Sept. 21
By Jesse Allen - 21 Sep, 2016 - Comments: 0

Mentor's Ricardo Anguiano takes a look at a proposal to prevent auto accidents from becoming pile-ups: the relaying of hazard information to the cloud and on to upcoming vehicles. Why get rid of 3.5mm audio jacks? Synopsys' Michael Posner says it's all about the power optimization in the upcoming USB Type-C digital audio specification. NXP's Anand Kannan also thinks Type-C should be the d... » read more

Plugging Holes In Machine Learning
By Ed Sperling - 19 Sep, 2016 - Comments: 0

The number of companies using machine learning is accelerating, but so far there are no tools to validate, verify and debug these systems. That presents a problem for the chipmakers and systems companies that increasingly rely on machine learning to optimize their technology because, at least for now, it creates the potential for errors that are extremely difficult to trace and fix. At the s... » read more

Blog Review: Sept. 14
By Jesse Allen - 14 Sep, 2016 - Comments: 0

Are wide bandgap lll-V power devices feasible? Applied's Ben Lee considers the challenges, and potential rewards, of silicon carbide and gallium nitride. DVCon India chair Gaurav Jalan chats with keynote speaker Alok Jain about the challenges of verifying complex SoCs, the unique verification needs of the IoT, and what might lie beyond UVM. From power intent abstraction to automatic power... » read more

Cars, Security, and HW/SW Co-Design
By Jeff Dorsch - 13 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Speeding Up Mask Production
By Mark LaPedus - 12 Sep, 2016 - Comments: 0

Chip production is becoming more complex and expensive at each node. As a result, chipmakers require a growing number of new manufacturing technologies to enable the next wave of devices at advanced nodes. In the fab, for example, the most obvious need is extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography. In addition, chipmakers also need a new class of atomic-level proces... » read more

Controlling Heat
By Ann Mutschler - 12 Sep, 2016 - Comments: 0

Modeling on-chip thermal characteristics and chip-package interactions is becoming much more critical for advanced designs, but how to get there isn't always clear. Every chip, based on its target application, has a thermal design power (TDP) target. This is the typical power it can consume without overreaching the acceptable thermal limits in its intended environment. But in order to rate t... » read more

The 2016 Wilson Research Group Functional Verification Study
By Harry Foster - 08 Sep, 2016 - Comments: 0

I am writing a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group functional verification study blogs, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons: Some of the more interesting trends in our 2016 study are related to F... » read more

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