Heterogeneous Multi-Core Headaches

By Ed Sperling - 28 Jan, 2016 - Comments: 4

Cache coherency is becoming more pervasive—and more problematic—as the number of heterogeneous cores used in designs continues to rise. Cache coherency is an extension of caching, which has been around since the 1970s. The notion of a cache has a long history of being utilized to speed up a computer's main memory without adding expensive new components. Cache coherency's introduction coi... » read more

Using Agile Methods For Hardware

By Ann Mutschler - 28 Jan, 2016 - Comments: 11

[getkc id="182" kc_name=agile development"] methodology for software is getting a much closer look by hardware teams these days, because what used to work in SoC design and verification isn't working nearly as well with rising complexity. Development processes need to be constantly evolved to determine how to be more productive, deliver higher quality, cut costs in development, and how to g... » read more

Three Steps To Complete Power-Aware Debug

By Ellie Burns - 28 Jan, 2016 - Comments: 0

In previous blogs, we’ve talked about UPF and the successive refinement low power flow developed by ARM and Mentor Graphics (you can find these here.) In this blog we’d like to walk through some typical debugging scenarios our customers face in their low power designs. So I’ve asked two of our low power debug experts, Gabriel Chidolue and Mark Handover, to join me to make sure you get ... » read more

Are Chips Getting More Reliable?

By Ed Sperling - 28 Jan, 2016 - Comments: 4

Reliability is emerging as a key metric in the semiconductor industry, alongside of power, performance and cost, but it also is becoming harder to measure and increasingly difficult to achieve. Most large semiconductor companies look at reliability in connection with consumer devices that last several years before they are replaced, but a big push into automotive, medical and industrial elec... » read more

Predictions For 2016: Tools and Flows

By Brian Bailey - 28 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Beyond UVM Registers — Better, Faster, Smarter

By Mentor, a Siemens Business - 27 Jan, 2016 - Comments: 0

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex syst... » read more

Debug: Last Bastion Of Automation

By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Blog Review: Jan. 27

By Jesse Allen - 27 Jan, 2016 - Comments: 0

There's an ocean of possibilities for transistors and interconnects at the 5nm node, says Cadence's Paul McLellan – but will any of them be feasible in time? How would you design R2-D2? Mentor's Joe Hupcey III lays out what low power techniques he thinks the Star Wars droid might require. It's not all clear skies in the world of FinFETs, as Synopsys' Graham Etchells continues his series... » read more

5nm Fab Challenges

By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

Automated Power Model Verification For Analog IPs

By Sierene Aymen - 21 Jan, 2016 - Comments: 0

By Sierene Aymen and Hartmut Marquardt Creating macro power models for analog intellectual property (IP) blocks is essential to enable the chip assembly group to effectively integrate these blocks within their place and route environment. These macro models, which define power domains, identify IP ports as signal, power, ground, or trivial ports, and describe the associations of signal pins ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Mentor Graphics