Predictions For 2016: Semiconductors, Manufacturing And Design

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Tech Talk: Double-Triple Patterning

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

The Future of Package Design Verification: Assembly Design Kits

By Mentor, a Siemens Business - 20 Jan, 2016 - Comments: 0

Chip design companies and package assembly houses have no unified signoff verification process to ensure that an IC package meets manufacturability and performance requirements. Packages need a process that confirms the disparate products they contain can be manufactured within a single package. Mentor Graphics collaborated with Qualcomm and STATS ChipPAC to develop a prototype assembly design ... » read more

Blog Review: Jan. 20

By Jesse Allen - 20 Jan, 2016 - Comments: 0

How far can you go on solar power? 493 million miles, at least if you're the Juno spacecraft. Plus, winemaking gets a boost from submarine technology, in this week's top tech picks from Ansys' Bill Vandermark. Mentor's Steve Pateras digs into how automotive ICs bring a whole new set of requirements that are driving the evolution of memory BIST. If you're interested in neural networks and ... » read more

Will 5nm Happen?

By Mark LaPedus - 20 Jan, 2016 - Comments: 7

Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

Manufacturing Bits: Jan. 19

By Mark LaPedus - 19 Jan, 2016 - Comments: 0

Bubble-pen lithography The University of Texas at Austin has developed a new nano-patterning technology--bubble-pen lithography. Researchers have devised a bubble-pen that enables optically-controlled microbubbles. The bubbles are used to pattern structures onto a surface at tiny dimensions. Bubble-pen lithography could be used in microelectronics, nanophotonics, and nanomedicine. In si... » read more

Bridging Hardware And Software

By Ann Mutschler - 18 Jan, 2016 - Comments: 1

Methodology and reuse are two fairly standard concepts when it comes to semiconductor design, but they're viewed completely differently by hardware and software teams. It's a given that hardware and software have different goals and opinions about how best to do design. And while all agree that a single methodology can pay dividends in future chips, there is disagreement over who should shap... » read more

Micro-Architectural Exploration for Low Power Design

By Abhishek Ranjan - 14 Jan, 2016 - Comments: 0

In the first part of this series, we had discussed the need to perform power optimizations and exploration at higher levels of abstractions where the potential to reduce the power consumption is highest. We presented the need for making coarser changes at higher level of abstractions to exploit full power saving potential. In the second part, we discussed some very potent micro-architectural te... » read more

More Uses For Hypervisors

By Ann Mutschler - 14 Jan, 2016 - Comments: 0

Hypervisors are showing up in more places than ever before as a quick and inexpensive way to utilize multiple cores and multiple chips more effectively and more securely. This marks an interesting twist for a technology that originally was developed as a way of enabling virtualization on a PC, allowing users to run multiple incompatible applications on the same computer. That was followed in... » read more

Predictions For 2016: Markets

By Brian Bailey - 14 Jan, 2016 - Comments: 0

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Mentor Graphics