Blog Review: Sept. 2


When it comes to cars, manufacturers may be adding too many features too fast, says Mentor's John Day. Up to half of the features may never get used either because they aren't useful or they are too complex. Cadence's Christine Young sat down with Neeti Bhatnagar, a software engineering group director to discuss the challenges and rewards of working in a distributed, cross-functional team, t... » read more

Making Hardware Design More Agile


Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Rethinking Differentiation


Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, w... » read more

Software Driving More Hardware Designs


The influence of software engineers is growing inside of chip and systems companies, reversing a decades-old trend of matching the software to the fastest or most power-efficient hardware and raising as-yet unanswered questions about what will change in SoC design. The shift is particularly evident in chips developed for high-volume markets such as mobile phones and tablets. It's also happen... » read more

The Trouble With Abstractions


Ask chip engineers about the value of abstractions and you're likely to get a spectrum of answers. While abstractions help in seeing the big picture on complex designs, the data for performance and power needs to be annotated from detailed information the engineering team may obtain later in the design flow. There is valuable information that can come from using abstractions correctly. And ... » read more

Full AMS Design Flow For The IoT


By Nicolas Williams and Jeff Miller The pressure for a new generation of (analog/mixed-signal) AMS design capabilities has been accelerated by the sudden demand for Internet of Things (IoT). These inexpensive devices are used in an expanding array of scenarios on the edge of the network — thus the demand for an AMS design environment that is affordable and easy to use, but powerful enough ... » read more

Full-Flow Tool Suite For Both Custom Analog And Mixed-Signal Designs


The Tanner EDA AMS IC design flow offers a cohesive, integrated mixed-signal design suite that is ideally suited to IoT and project-based design with its extremely short cycle times and sensitivity to cost. Learn more about the Tanner AMS solution in this white paper. To read more, click here. » read more

Blog Review: Aug. 26


Synopsys' Marc Greenberg attended IDF and learned more about the newly announced Intel/Micron 3D XPoint memory technology named Optane including initial ship dates and some implementation details. In concluding his analysis of the 2014 Functional Verification Study, Mentor's Harry Foster reveals an unexpected finding about design size and respins. How do you keep your power grid from bein... » read more

Who’s Calling The Shots


As discussed in part one of this report, OEMs are making more of the decisions about what goes into a system design. A large part of this shift involves software, which falls on many plates throughout the ecosystem. Making sure all of the layers of software interoperate and integrate well together is no small feat, and it is growing in complexity at every turn as systems becomes more sophist... » read more

The Week In Review: Design/IoT


Chips Rambus moved into the fabless market with the announcement that it is developing memory controller chips, expanding the company's business beyond just creating IP for the memory and security markets. Read Ed Sperling's full analysis. Standards Accellera updated the Standard Co-Emulation Modeling Interface (SCE-MI). The newest version of the standard, SCE-MI 2.3, expands the set o... » read more

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