Rethinking Differentiation

What makes one semiconductor design stand out from another?


Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers.

The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, which has been critical since the advent of the smart phone and the rise of the fabless model, are no guarantees of success.

Several key factors have contributed to this disruption:

1. Consolidation of IP vendors and chipmakers has increased the reliance on integrated third-party IP blocks, subsystems and platforms. While there are plenty of choices, the same choices are available for most chipmakers.
2. The rising cost and complexity of developing chips at the most advanced process nodes is slowing down the migration. Even if the move from 28nm to 16/14nm can improve performance and reduce leakage current, dynamic power is a growing problem that can impact everything from reliability to electromigration. And at 10nm and beyond, there are so many new challenges with RC delay in interconnects, multi-patterning, new transistor structures, and new materials, that companies are beginning to explore other options such as 2.5D and 3D IC architectures and FD-SOI. This certainly makes for some tough choices on the part of the entire ecosystem about which way to move forward—process, architecture, insource versus outsource.
3. With complex SoCs, differentiation gets even murkier. Rather than emphasizing performance of an application processor for a smart phone or the number of cores, the focus may be on optimizing the performance of a specific function, which is not the main selling point of any device. And instead of average power consumption, the focus is on power budgets for those portions of the chips that are most likely to be lit up rather than the overall chip’s power budget because 90% of the silicon may remain dark most of the time.

These are subtle but important changes in priorities because the focus is on a combination of value to the customer and to the customer’s customer. When that value becomes diffuse, as it has within a complex design, it’s much more difficult to differentiate one end device from the next. That is part of the reason there has been so much emphasis on software lately.

“Software is what makes the difference,” said Zibi Zalewski, general manager of the hardware division at Aldec. “Hardware platforms have become more or less similar, while software layers and apps can transform those platforms into different devices and products. If you look at the current group of available chips, they come with a wide portfolio of built-in interfaces and peripherals, which lets them work as a universal platform for different functions and markets. It’s the software that can determine whether those chips go into a smartphone or a car multimedia system controller.”

He’s not alone in that view, but it does require some serious thought about what makes a successful business model for the future.

“There are a lot of people trying to fulfill the same function in widely different ways,” said Charlie Janac, chairman and CEO of Arteris. “So if you look at an application processor, that differentiation can come from the process—16/14nm is going to have more performance than 20nm. It can come from an innovative subsystem and how effectively the SoC is connected together. And it can come from the software.”

Janac noted that future success will be defined by whoever can best take advantage of these shifts.

“All of these changes mean there will be big winners and losers,” said Janac. “IP suppliers have to understand the chip architect. The chip companies have to understand software and the software business model. And the software developer has to understand the overall business model. People who can figure this out will do very well. But if you look back at what happened in the PC business, most of the PC guys didn’t build anything new. There was a lack of innovation and stagnation. The ability to innovate is where the value has always been, and whoever captures the innovation dollars in the SoC business wins.”

Whether that happens in hardware, software, IP or even business models is unknown at this point because so much is in flux. But there are certainly plenty of options for different combinations, and no shortage of companies willing to try.

Consider Andes Technology, whose business model is based on mixing up various ingredients, combining ultra low-power cores with security and a software stack as a way of standing out from the pack. It has been successful so far using this model, particularly in the IoT space where hardware serves as a platform for the software and battery life is critical because the devices are always on.

“When our customers come to us usually they demand low power, low cost, and a small code size,” said Frankwell Lin, Andes’ president. “We guarantee our customers can reproduce the numbers we publish, and we guarantee 20% to 40% power savings over our customers. That combines four parameters—power, size, clock frequency and performance. Each core is 50% to 150% more efficient.”

Microchip has seen the same trends. While the company sells advanced 16- and 32-bit microcontrollers, it’s still investing heavily in 8-bit MCUs. Greg Robinson, 8-bit MCU marketing director, said the core is not as much of a differentiating factor as the architecture—throughput, ability to continue doing work while the chip is mostly asleep, and overall power budget.

Consolidation fallout
One variable in this equation involves the number of companies developing hardware. As that number decreases—particularly large companies in high-profile M&A deals such as Intel-Altera, NXP-Freescale and Avago-Broadcom—the overall R&D budget of the semiconductor industry could come under pressure.

While this type of activity traditionally has favored third-party IP—it’s quicker to buy than to build the missing pieces—in this case it may be partly caused by the IP market. The amount of IP needed for a complex SoC is growing to the point where only the largest companies can afford to buy it, and even fewer can afford to build it.

“From my standpoint, consolidation has to do with an increasing in NRE and an ability to acquire IP,” said Chi-Ping Hsu, senior vice president and chief strategy officer at Cadence. “What a chip company originally made is now only a block on an SoC, and the IP business is not easy. If you think about all the fabless IP companies that were formed, most are now gone. They either were not able to make money or they were acquired by Cadence and Synopsys.”

He said the big challenge today isn’t just making IP, it’s integrating it with other IP, which also becoming increasingly difficult. This is where subsystems were supposed to fit in, but that hasn’t happened at the rate anyone expected. “One of the reasons subsystems haven’t taken off is that no two applications are the same, and a subsystem has to be guaranteed to work. We haven’t seen a subsystem that you can take off the shelf and use everywhere.”

The alternative is to use a sub-optimized ASSP or FPGA, which doesn’t help with differentiation, Hsu noted.

There is a fair amount of debate over this topic. Drew Wingard, CTO at Sonics, believes more IP is being pre-integrated. Whether that’s a subsystem, or it’s called something else, is a matter of semantics.

“IP providers are providing a more complete solution,” Wingard said.
While he agrees there is no way to make that IP more general purpose, it can be optimized or tuned by the customer. He added that the goal of consolidation is not to bring more technology in-house. Instead, it is to focus on specific areas where companies can add value.

Different structures
Differentiation can come from many directions. Two companies can take different logic, memory, and IP blocks and create comparable chips. But they also can take the same pieces and come up with completely different chips.

This is particularly true with different architectures such as 2.5D and 3D stacked die, where the benefits of reduced power and improved throughput are driving new designs.

“This is a new agenda,” said Mike Gianfagna, vice president of marketing at eSilicon. “It requires a lot of collaboration across suppliers involving systems, packaging, interposers, whether those are silicon or organic. But the companies that can integrate all of these effectively have an advantage. There is talk that this is more expensive, but cost is an artifact of yield learning. We’ve done a number of designs in 2.5D already and it’s a different frontier. It’s not just a cheaper way of doing things in the future. It may be the only way for power and performance.”

The secret isn’t just in how the pieces are put together, though, whether that’s in stacked die or planar configurations. It’s also in the pieces themselves. Big chip and systems companies have been able to win support from IP companies to modify what is considered standard IP.

“It’s not unusual for the biggest companies, which are the market leaders, to request features that are not in the specs,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “That’s what gives them their competitive edge. These are companies that drive the product definition.”

He said those companies also are likely to work much more closely with the service organizations of IP vendors to come up with a unique version of the IP. “If you’re looking at USB or any other standards-based interfaces, there is a lot of difference between what one vendor implements versus another.”

Differentiating with business models
Technology isn’t the only way to differentiate a design, though, even in a technology-driven field. Cost has always been a key consideration, particularly for companies that were not the market leaders in technology. Selling a chip one process node behind Intel was always lucrative for AMD and some of the RISC vendors in the PC days, and in smart phones companies such as HiSilicon, MediaTek and even Intel‘s Atom.

Price isn’t the only differentiator here, though. Time to market has become particularly important in constantly refreshing markets, particularly those dominated by the . In addition, being able to win a slot in a design that will last for years, such as in the automotive, mil/aero or industrial markets can help prop up a company to differentiate in other markets.

But in a complex ecosystem, it’s not just the chip that drives the differentiation. The foundry has to be there to support it, and the foundry business depends on the ability to run efficiently—particularly at advanced nodes where the investments in process technology and equipment can cost upward of $10 billion per node.

“We’re seeing several markets,” said Michael Buehler-Garcia, senior director of marketing at Mentor Graphics. “One is the IoT. The other is the growth of advanced nodes for Big Data, which is still driving big chips. The variable in between is the consumer telecom business, which is driving volume at advanced nodes. The challenge is betting on individual companies winning in order to fill the fab. Only one guy wins at that business.”

That’s a lot different at established process nodes, where one chipmaker doesn’t make much difference. Ironically, this is also the place where much of the innovation is happening these days, said Buehler-Garcia, because the race isn’t just to the next process node. The same power-domain techniques are available at 40 and 55nm as at 16/14nm, for example, but time to market is faster, NRE costs are lower and the tools and processes have been used for so long that there are very few remaining bugs.

What isn’t working so well anymore is the superchip SoC model. While incredibly efficient and different when it was first created, the model has actually restricted innovation over time.

“The problem with the SoC model is that an SoC may be sold as a standard product to 10 to 50 customers,” said Drew Wingard, CTO at Sonics. “The silicon companies define a large chunk of the system and they create system value, but they don’t capture it. The system company does derive system value, but in most cases they’re not willing to share it. So there’s a gap there. What if that gap widens? Either the silicon guys work out strategic relationships where the system vendors pay more, or the system guys go back to ASICs.”

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