Are More Processor Cores Better?


Up until the early 2000s, each generation of processor was faster, used more exotic architectures, had deeper pipelines, used more transistors, ran at higher clock frequencies and consumed more power. In fact power was rising faster than performance and led to the extrapolation that within a few generations, processors would run as hot as nuclear reactors. Something had to change, and that c... » read more

Another Tool In The Bag


Clocks can account for 25% to 40% of total dynamic power consumption in a complex chip, so when looking for areas to reduce power, the clock tree network is a good place to start. Structurally, it is certainly possible to have single-bit flip flops with a clock that connects to every one of the flip flops, and the power in general is proportional to the number of buffers in the clock tree on... » read more

The Week In Review: Design/IoT


Chips NXP rolled out what it claims are the most power-efficient microcontrollers for always-on applications. The minimum draw is 3 microamps for continuous sensor listening. Tools Mentor Graphics beefed up its CFD tool, adding thermo-fluid analysis simulation capabilities for automotive, aerospace and industrial applications. Included is support for FMI, an open-source environment that al... » read more

Keeping Up With The Productivity Challenge


Until recently, EDA software rode the coattails of increasing processor performance as part of its drive to continue providing faster and more powerful development software to the people designing, among other things, the next generation of faster processors. It was a fortuitous ring. Around the turn of the century, with the migration to multi-core computing systems, all of that changed. In ord... » read more

Blog Review: Nov. 5


Cadence's Brian Fuller zeroes in on ISO 26262, the automotive safety standard that's supposed to guard against nightmare failures in your car. Hopefully it works. They won't protect against cyber terrorism, though. Rambus' Aharon Etengoff takes a look at the challenges of connected vehicles. Mentor's J. Van Domelen looks at NASA's increased reliance on commercial partners, which has not b... » read more

Three Challenges Impacting The Efficiency Of PCB Engineering Teams


We live in an era of rapidly accelerating design complexity, with designs often doubling in performance and/or capacity between board revisions. At the same time, we’re seeing a shift in the workforce, particularly in the older design markets of the United States and Europe. Finally, we live in an era where everything’s a system—the days of standalone, single-board projects are gone. Cons... » read more

Design Rules Explode At New Nodes


Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

The Week In Review: Design


Tools Mentor Graphics rolled out an extension to its PCB design platform that allows for synchronization of processes across multi-board systems. The new tool captures logic and system definitions for boards, cables, backplanes, cable assemblies, sensors and actuators. Cadence introduced a dynamic characterization solution for mixed signal blocks such as PLLs, data converters, high-speed tr... » read more

Week 21 – Visiting Detroit


Who would have thought I’d end up sitting outside in the sunshine in downtown Detroit writing the first draft for my next blog. I’m here with a few of my Mentor colleagues to attend SAE Convergence and to have a discussion with GM about a possible DAC keynote. Stay tuned (and keep your fingers crossed) — I hope to tell you more about that at a later time. SAE Convergence is a two-day conf... » read more

A Dream For The Future Of Real System-Level Design Validation


"I have a dream…that one day…all SoCs will be free…of bugs and verifying them will be a walk in the park. I have a dream…that one day…all software engineers will be able to validate their software on pre-silicon hardware at the speed of light, delivering fully functional embedded software “before-on-time” for tape-out. I have a dream today…Well, if not today, how about first ... » read more

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