tag: Mentor Graphics

Blog Review: Oct. 29
By Ed Sperling - 29 Oct, 2014 - Comments: 0

Ansys' Bill Vandermark uncovers the top engineering articles for the week. Check out the tractor beam in Australia that can push and pull objects and Naim's soundbar that may act like a gateway drug to bankruptcy. It may sound counterintuitive, but ARM's Jakub Lamik draws a direct link between bandwidth consumption and power consumption and explains that's the case. Samsung's Farhad Tab... » read more

Week 20: Marketing Musings
By Anne Cirkel - 24 Oct, 2014 - Comments: 0

Last week I was on vacation in Pacific City at the Oregon Coast. We usually take our dogs there twice a year. They love the freedom to roam around on McPhillips Beach, less crowded than other beaches in the area, and we usually take them a couple of times up Cape Kiwanda’s Great Dune, more than 200 feet up. We were amazed how warm it still was and not just from the work of climbing the dune. ... » read more

The Week In Review: Design
By Ed Sperling - 24 Oct, 2014 - Comments: 0

IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

2.5D Timetable Coming Into Focus
By Ed Sperling - 23 Oct, 2014 - Comments: 0

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Advanced Nodes Drive Changing EDA Requirements
By Ann Mutschler - 23 Oct, 2014 - Comments: 0

With new technical requirements of today’s bleeding edge manufacturing processes propelling the ecosystem of semiconductor foundries, EDA tool suppliers and IP developers, work is being done behind the scenes like a well-conducted orchestra to make sure customer designs can flow through a foundry when the time comes. One of the areas in the design process where new processes are felt acute... » read more

How Many Levels Of Abstraction Are Needed?
By Jon McDonald - 23 Oct, 2014 - Comments: 0

Recently I was having a conversation with a user who was creating cycle accurate SystemC models. My initial thought was, "Why would this be necessary?" Through the course of discussions I realized that he did have a design questions that required that level of accuracy and the simulation performance trade-offs were appropriate for his needs. His cycle accurate SystemC models were running at abo... » read more

Legal Battlefield In Emulation
By Brian Bailey - 23 Oct, 2014 - Comments: 1

Given the rate of research and development within the EDA industry, you might expect it to be a highly litigious industry, but apart from theft claims, there have not been that many law suits brought to bear – except in the area of [getkc id="30" comment="emulation"]. Emulation has, since its early days in the early 1990s, always been a legal battlefield, and the hostilities continue to this ... » read more

When To Use Simulation, When To Use Emulation
By Mentor, a Siemens Business - 22 Oct, 2014 - Comments: 0

Should you emulate or simulate? In this brief historical review, Dr. Lauro Rizzatti compares the two and reveals when to use which and explains why only emulation can verify embedded SW in an SoC design. To read more, click here. » read more

Blog Review: Oct. 22
By Ed Sperling - 22 Oct, 2014 - Comments: 0

What is UX? The User Experience, of course. Rambus' Aharon Etengoff notes that the IoT UX is now the subject of a Harvard Business Review article. A long list of hurdles are expected at the 10nm process node, including multiple levels of local interconnects, more complex layout rules, timing problems, and a slew of others. Cadence's Richard Goering puts it all in perspective. Mentor's R... » read more

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