tag: Mentor

Blog Review: Nov. 17
By Jesse Allen - 17 Nov, 2021 - Comments: 0

In a podcast, Arm's Geof Wheelwright and Hilary Tam chat about the importance of efforts to decarbonize compute and how low-power compute can help ensure that the benefits of technology outweigh the environmental cost. Synopsys' Graham Allan and Vikas Gautam consider what's driving demand for HBM3, what's different from the previous HBM2E specification, unique design considerations, and how ... » read more

AI/ML Workloads Need Extra Security
By Bryon Moyer - 15 Nov, 2021 - Comments: 0

The need for security is pervading all electronic systems. But given the growth in data-center machine-learning computing, which deals with extremely valuable data, some companies are paying particular attention to handling that data securely. All of the usual data-center security solutions must be brought to bear, but extra effort is needed to ensure that models and data sets are protected ... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 12 Nov, 2021 - Comments: 0

Automotive The U.S. Congress passed an infrastructure bill that includes mandates for the U.S. automobiles to install technology in new vehicles that will stop impaired drivers from driving a vehicle. Sec. 24220, the advanced impaired driving technology section of the bill says the Secretary of Transportation is responsible for coming up with standards after which the auto industry has at the ... » read more

Two Methods For Debugging SW Workloads On Arm-Based SoCs
By Andy Meier - 11 Nov, 2021 - Comments: 0

By Andy Meier and Tomasz Piekarz In a typical system-on-a-chip (SoC) development project, chip architects will make a given SoC's initial specification available to design teams years in advance of the silicon. As requirements change, they will modify both the hardware and software specifications. Typically, a large portion of the software development occurs much later in the development pro... » read more

Aprisa Place-And-Route For Low-Power SoCs
By Siemens EDA - 10 Nov, 2021 - Comments: 0

The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

Debugging Embedded Applications
By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

Blog Review: Nov. 10
By Jesse Allen - 10 Nov, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Malcolm Penn of Future Horizons explains key reasons behind the cyclical nature of the semiconductor industry and how the root of the current chip shortage problems goes back to before the pandemic. Siemens EDA's Ray Salemi continues investigating using Python for verification with a look at some UVM utilities and how they would be used in Python. Syn... » read more

Enablers And Barriers For Connecting Diverse Data
By Anne Meixner - 09 Nov, 2021 - Comments: 0

More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Reversible Chain Diagnosis
By Siemens EDA - 09 Nov, 2021 - Comments: 0

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture. This paper describes the novel scan chain architecture t... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

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