tag: Mentor

Blog Review: June 12
By Jesse Allen - 12 Jun, 2024 - Comments: 0

Cadence's Deep Mehta finds that PCIe 6.0 switches need advanced verification strategies that delve deeper than basic functionality, such as generating backpressure traffic to identify potential performance bottlenecks and ensure the switch operates optimally in real-world scenarios. Siemens' Reetika explains why proper management and verification of reset domain crossing (RDC) paths are cruc... » read more

Chip Industry Week In Review
By The SE Staff - 07 Jun, 2024 - Comments: 0

Rapidus and IBM are jointly developing mass production capabilities for chiplet-based advanced packages. The collaboration builds on an existing agreement to develop 2nm process technology. Vanguard and NXP will jointly establish VisionPower Semiconductor Manufacturing Company (VSMC) in Singapore to build a $7.8 billion, 12-inch wafer plant. This is part of a global supply chain shift “Out... » read more

The Uncertainty Of Certifying AI For Automotive
By Ann Mutschler - 06 Jun, 2024 - Comments: 1

Nearly every new vehicle sold uses AI to make some decisions, but so far there is no consistency in what is being developed, where it is being used, and whether it is compatible with other vehicles on the road. This fragmentation is partially due to the fact that AI is still a nascent technology, and cars and trucks sold today may be significantly different than those that will be sold sever... » read more

Why It’s So Hard To Secure AI Chips
By Adam Kovac - 06 Jun, 2024 - Comments: 0

Demand for high-performance chips designed specifically for AI applications is spiking, driven by massive interest in generative AI at the edge and in the data center, but the rapid growth in this sector also is raising concerns about the security of these devices and the data they process. Generative AI — whether it's OpenAI’s ChatGPT, Anthropic’s Claude, or xAI’s Grok — sifts thr... » read more

Toward A Software-Defined Hardware World
By Karen Heyman - 06 Jun, 2024 - Comments: 0

Software-defined hardware may be the ultimate Shift Left approach as chip design grows closer to true co-design than ever with potential capacity baked into the hardware, and greater functionality delivered over the air or via a software update. This marks another advance in the quest for lower power, one that’s so revolutionary that it’s upending traditional ideas about model-based systems... » read more

Techniques To Identify Reset Metastability Due To Soft Resets
By Siemens EDA - 05 Jun, 2024 - Comments: 0

Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. These complex reset architectures with multiple reset domains, ensure functional recovery from hardware failures and unexpected electronic faults. But the transmission of data across sequential elements that are reset by different asynchronous and soft reset ... » read more

Blog Review: June 5
By Jesse Allen - 05 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh provides an overview of the low power entry and exit flows in USB4 Version 2.0 link speed and how they have been simplified by making low power entry uni-directional and removing the need for certain handshakes for low power exit of the re-timers. In a podcast, Siemens' Steph Chavez chats with Daniel Beeker of NXP about the foundational importance of power distributio... » read more

Why IC Design Safety Nets Have Limits
By Ann Mutschler and Adam Kovac - 04 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss different responsibilities in design teams and future changes in tools with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager at Siemens EDA; Dirk Seynhaeve, vice president of business development at Sigasi; Simon Davidmann, formerly... » read more

Ensuring Your Power And Ground Nets Are Correctly Connected
By Terry Meeks - 03 Jun, 2024 - Comments: 0

In most chip designs, the power and ground nets are likely your largest and most important nets. If any devices are not properly connected, then you cannot expect them to function as expected. Amongst the many problems that can occur to power and ground involves the connections to the well areas of your design that power all the bulk connections to your devices. Well regions connectivity is oft... » read more

Chip Design Digs Deeper Into AI
By Ann Mutschler - 03 Jun, 2024 - Comments: 0

Growing demand for blazing fast and extremely dense multi-chiplet systems are pushing chip design deeper into AI, which increasingly is viewed as the best solution for sifting through scores of possible configurations, constraints, and variables in the least amount of time. This shift has broad implications for the future of chip design. In the past, collaborations typically involved the chi... » read more

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