The Next Big Thing


Sometimes, we spend so much time looking for the next big thing that we actually miss something even bigger. I have to admit I was guilty of this while employed by a large EDA company 20 years ago. I was one of those ESL people — Electronic System Level acolytes, with Gary Smith as our standard bearer. We wanted to do many things, including raising the level of abstraction for design and veri... » read more

Chip Industry Week in Review


San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops


As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s architectures often juggle multiple asynchronous reset sources alongside sequential elements such as non-resettable registers (NRRs), which operate without dedicated reset pins. When a signal crosses... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking


Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

Even With AI Inroads, Human Chip Designers Still Essential


The proliferation of AI tools seems perfectly matched to fill a talent shortage, but a closer look shows the skills do not entirely overlap. Certain parts of the EDA pipeline require human engineers, and it seems likely to stay that way for the foreseeable future. The dark art of analog design, the final word on safety-critical functional safety, high-level architectural decisions, product i... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops


The importance of reset domain crossing (RDC) verification in ensuring robust and reliable SoC operation cannot be overstated. Verification tools for RDCs are essential in identifying potential metastability issues and ensuring that signal transitions across reset domains are properly handled. This paper presents a novel approach to tackling the challenges of RDC verification involving non-rese... » read more

Advances In Formal Verification Technology


Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Blog Review: Oct. 29


Siemens' Ujjwal Negi and Prashant Dixit warn that while UCIe 3.0 improves performance and efficiency through higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, those enhancements also increase verification complexity. Cadence's Anika Sunda suggests that a unified digital thread that connects verification environ... » read more

Unlocking Clarity: Keyphrase Trees Bring Structure To AI Text Analysis


By Amr Hegazy, Mohamed Abdelkarim, and Reem El Adawi In the vast digital landscape of information, from intricate design specifications to extensive patent literature and complex verification reports, extracting meaningful insights often feels like searching for a needle in a haystack. This challenge is particularly acute in the semiconductor industry, where critical details are buried with... » read more

Chip Industry Week in Review


Retaliations and countermoves leading up to planned trade talks between the U.S. and China led experts to wonder, 'Who's winning?' New activity on this front: China issued questionnaires to some U.S. semiconductor firms as part of an anti-dumping probe, demanding detailed data on sales, profit margins, logistics costs and Chinese customer names for analog chips. The probe appears aimed at ... » read more

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