Digital Twins For Packaging: Bridging Design, Fab, Test, And Reliability


Digital twins dominated discussions at SEMICON West this year, appearing in keynote presentations, panel sessions, and workshops. The conversation reflected a noticeable shift in how the industry views the technology. What once was mainly associated with design exploration now spans the manufacturing lifecycle. In packaging and assembly, digital twins are emerging as a way to connect design ... » read more

Powering Efficiency: AI Transforms IC Manufacturing As ICs Fuel AI


The push to grow today’s $500 billion-plus semiconductor industry to $1 trillion in annual revenue is challenging every aspect of the broader supply chain to embrace AI. Artificial intelligence is transforming the way fabs are architected and run, how devices are manufactured, and how server farms are constructed going forward. At the same time, all of this is being enabled by advancements... » read more

Multiple Challenges Emerge With Physical AI System Design


Physical AI holds the promise of making everything from robots to a slew of mobile edge devices much more interactive and useful, but it will significantly alter how systems are designed, verified, and monitored. Physical AI systems need to work both independently and together. They need the ability to make decisions quickly and locally, typically using much less power than other types of AI... » read more

Blog Review: Oct. 22


Cadence's Sandip Sadadiya shows what's new in the AMBA AXI Issue L protocol update, which introduces a new credit-based transport mechanism that replaces the traditional VALID/READY handshake, along with improved flow control mechanisms. Siemens' Farhad Ahmed highlights the growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way and intro... » read more

In-System Test For AI Data Centers


Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

Startup Tips To Get From Seed Funding To Series A, B, C


Startups are often created by experienced engineers who figure out how to solve a technical problem they are dealing with at work, or by PhD candidates in research labs before they have even started their first full-time job. Either way, getting seed money to the tune of a few million dollars is relatively easy compared to securing further rounds of funding and achieving the company’s exit go... » read more

Current Problems Grow For Power Delivery


IR drop is becoming more problematic for a growing proportion of designs, an indication that the power delivery network (PDN) is not providing enough current to parts of the design when required. Unfortunately, there is no easy fix to this problem. In the past, when voltages were much higher, a small voltage droop didn't really matter. At the same time, wires were much thicker and presented ... » read more

Frequency-Impedence Verification Of Power Delivery Network With HyperLynx PI For AMD Versal Adaptive SoC Devices


HyperLynx Decoupling analysis and the PDN Decoupling Optimizer are powerful tools for exploring various PDN structures and decoupling strategies. This paper presents a study showcasing the advantages of performing a HyperLynx decoupling analysis to verify PDN performance, and it highlights the extensive collaboration between Siemens and AMD in creating a complete system design flow for performi... » read more

New Frontiers In Fault Detection And Classification


IC manufacturers are increasingly relying on intelligent data processing to prevent downtime, improve yields, and reduce scrap. They are integrating that with fault detection and classification (FDC) to trace faults to their cause. Today’s FDC systems feature better sensors, variability control, and both predictive and prescriptive modeling. In the future, FDC will enable real-time decisio... » read more

Revolutionizing Chip Testing: Navigating Bottlenecks


In today's rapidly evolving semiconductor landscape, System-on-Chips (SoCs) are becoming increasingly complex, integrating multiple processing cores, specialized accelerators and vast memory arrays. This escalating complexity, while enabling incredible functionality, presents significant challenges for Design-for-Test (DFT) engineers. Ensuring the thorough and efficient testing of these intrica... » read more

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