DFT At The Leading Edge


Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

Startup Challenges In A Changing EDA World


The Electronic Design Automation (EDA) industry is a mature industry, but it's also one that is constantly changing. Each process node and packaging technology advancement places new demands and constraints on existing tools. In addition, changing design problems and paradigms transform how design teams operate, and the goals they target. For a relatively small industry, EDA requires a dispr... » read more

Edge And IoT Security Turning A Corner


Security is beginning to improve for a wide range of IoT and edge devices due to better tools, the implementation of new standards and methodologies, and an increasing level of collaboration and communication across different market segments that in the past had little or no interaction. Until recently, many vendors in cost-sensitive markets offered the bare minimum of security. To make matt... » read more

How Software-Defined Vehicles Change Auto Chip Design


The shift to software-defined vehicles is changing nearly every aspect of automotive design, from what hardware is added into vehicles, when it gets added, and what gets left behind. Moving key features to software rather than hardware allows carmakers to bring new features to market faster, at a lower cost, and to modify those features more quickly. It is also expected to drive up the value... » read more

ISO 26262’s Importance Widens Beyond Automotive


The ISO 26262 standard, which has become a mainstay since the trend toward vehicle electrification really took root a decade ago, is starting to gain traction in markets outside of automotive chip and system design. At the center of this expansion is a focus on safety under a variety of conditions — extreme temperatures, unexpected vibration, or a collision that is unavoidable. This includ... » read more

Averting Hacks Of PCIe Transport Using CMA/SPDM


This paper describes the component measurement and authentication (CMA) and security protocol and data model (SPDM) flow used to establish the secure channels required for the transmission of encrypted packets. The various approaches, namely the symmetric and asymmetric flows, will be discussed in establishing a secure connection with the implementation of CMA/SPDM packets through data objects.... » read more

Tackling Reliability In Early IC Design


As the semiconductor industry continues its relentless march towards smaller process nodes and more complex integrated circuits (ICs), the challenge of ensuring reliability has become increasingly difficult. Industry analysts predict a significant increase in demand for semiconductor reliability verification as analysis become critical parts of the overall design verification process. The st... » read more

Blog Review: Jan. 8


Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

Chip Industry Week In Review


Updated for 12/20 government fundings and 12/23 for China trade investigation announcements. President Biden announced a trade investigation into "China's unfair trade practices in the semiconductor sector."  The announcement stated "PRC semiconductors often enter the U.S. market as a component of finished goods. This Section 301 investigation will examine a broad range of the PRC’s non-m... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier


In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

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