Cloud vs. Edge Gaming: Performance Gap Is Shrinking


Chip designers and gaming companies are scrambling to figure out whether the gaming market will tilt toward the cloud, the edge, or some combination of both. Multi-gigabit internet allows more people to play high-end games in the cloud, but edge-based gaming consoles and devices remain well-rooted, more secure, and private. Which one wins? So far, there are more questions than answers. Handh... » read more

Calibre 3DStress: Advanced Stress Analysis For Reliable 3D IC Design


As the industry transitions toward advanced 3D IC architectures and heterogeneous integration, managing thermo-mechanical stress is essential for product quality and long-term reliability. Calibre 3DStress enables design and packaging teams to simulate, analyze and disposition stresses imparted on the chip during or after the packaging process, ensuring that potential failure risks—such as wa... » read more

Blog Review: September 3


Cadence's Sriram Sharma Kalluri compares convolutional neural networks (CNNs) and transformers to show how their different architectures give them particular strengths and why the choice between them depends on the specific task, the available data, and the computational resources. Siemens' John McMillan provides a primer on the major IC package types, how they influence system design, therm... » read more

AI’s Value In Chip Design Depends On Data Availability


Experts at the Table: Semiconductor Engineering sat down to discuss the advantages and challenges in using AI in designing chips, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir ... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Government Funding For Chip Design Tools Spreads


Governments around the globe are starting to invest more heavily in chip design tools and related research as part of an effort to boost on-shore chip production, opening new opportunities for startups and established EDA companies. Those cash infusions, which are being doled out in the U.S., Europe, and Asia, are part of a growing recognition of the importance of design automation tools wit... » read more

Silicon Lifecycle Management Gains Traction, But It’s Complicated


Silicon lifecycle management (SLM) is gaining ground in semiconductor design and test by leveraging specialized on-die sensors and analytics engines to improve power, performance, yield, and reliability. Most modern SoCs mitigate the guesswork by leveraging DFT, which includes adding memory built-in self-test (BiST) or improving functional coverage, but these tests were meant for verifying c... » read more

How To Transform Verification Time-To-Results


The clock is ticking. Your team has just completed another full-chip DRC run on a complex 5nm SoC, and the results are overwhelming: millions of violations across hundreds of blocks. With tape-out deadlines approaching, you need to quickly identify which issues are critical, which are systematic and which blocks require immediate attention. Every day spent in DRC debug is a day delayed to marke... » read more

Verification Fails To Keep Up


Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Physical Access Control Raises New Security Concerns


Experts At The Table: Semiconductor Engineering sat down to discuss hardware security challenges, including fundamental security of GenAI, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit... » read more

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