Blog Review: September 3

Cadence’s Sriram Sharma Kalluri compares convolutional neural networks (CNNs) and transformers to show how their different architectures give them particular strengths and why the choice between them depends on the specific task, the available data, and the computational resources.

Siemens’ John McMillan provides a primer on the major IC package types, how they influence system design, thermal performance, and manufacturability, and why selecting the best one depends on the key tradeoffs involved for specific application requirements.

Synopsys’ Adrian Ng highlights a collaboration with the Thai Embedded Systems Association to facilitate AIoT chip prototyping and curriculum development with the aim of establishing Thailand as a regional hub for edge chip design.

Keysight’s Roberto Piacentini Filho warns that development process issues, such as questions about version control, IP metadata, and design data, can slash productivity and suggests deploying design data management tools to provide a single centralized source of truth for all information about every IP, SoC, and chiplet.

Arm’s Odin Shen shows how functional safety, containerized workloads, and Data Distribution Service-based real-time communication form the foundation of a resilient automotive system.

Infineon’s Steve Hanna highlights security improvements in the Matter smart home specification, including certificate revocation for cloned counterfeit devices and access restriction lists to limit which devices can change sensitive network configuration settings.

Ansys’ Susan Coleman and Emily Gerken find that using simulation tools in the classroom is becoming a key part of engineering education and helps capture students’ attention by enabling them to study real-world phenomena central to industry applications.

The ESD Alliance’s Bob Smith chats with John Kibarian of PDF Solutions about why collaboration is key to growing the semiconductor industry and the role of automated AI agents in handling the vast amounts of data created by multiple stakeholders throughout the process.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey takes issue with the economics of current AI development.

Synopsys’ Robert Kruger explores the myriad decisions multi-die chip designers face, from node selection to choice of interconnect.

Alphawave Semi’s Tony Chan Carusone looks at FEC performance in a variety of application scenarios.

Baya Systems’ Brian Carlson explains how profiling systems early can expose fundamental issues in data flow and resource coordination.

Cadence’s Guo Yu digs into using non-PCIe protocols for abstraction layers.

Siemens’ Priyank Jain shows how AI-driven DRC debug can overcome the chip integration bottleneck.

Keysight’s Yiao Li focuses on derivative-free compact modeling techniques for solving problems where gradient-based methods fall short.

Arteris’ Andy Nightingale talks about a standards-based approach to developing modular architectures for AI, HPC, and automotive platforms.