tag: Mentor

Week In Review: Design, Low Power
By Jesse Allen - 30 Jun, 2023 - Comments: 0

Keysight Technologies said it intends to acquire ESI Group for €913 million (~$998.6 million). ESI Group provides virtual prototyping solutions for the automotive and aerospace end markets that can create real-time digital twins to simulate a product's behavior during testing and real-life use. MLCommons announced the latest results from two MLPerf benchmark suites. One aims to measure the... » read more

Challenges Grow For Data Management And Sharing In EDA
By Ed Sperling - 29 Jun, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about more openness in EDA data, how increased complexity is affecting time to working silicon, and the impact of geopolitics, with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business U... » read more

Blog Review: June 28
By Jesse Allen - 28 Jun, 2023 - Comments: 0

In a podcast, Siemens' Spencer Acain discusses the role of AI and machine learning in IC verification and how it could help address noise by analyzing different signals from the diagnosis data to figure out the real root cause of a failure. Synopsys' Ian Land and Ron DiGiuseppe find that designers of aerospace microelectronics are applying lessons and technologies learned from the automotive... » read more

New Age Solution For Data Integrity And Authenticity
By Om Prakash - 27 Jun, 2023 - Comments: 0

With the advent of faster processing chips, the rate of data transfer has increased enormously. Be it artificial intelligence (AI), the Internet of Things (IOT), compute intensive analytics, or cloud computing, the demand for processing data in a fraction of a second is huge. Chips with superfast computing capabilities are used in applications where malfunctions can be life threatening, such as... » read more

Not All There: Heterogeneous Multiprocessor Design Tools
By Brian Bailey - 26 Jun, 2023 - Comments: 0

The design, implementation, and programming of multicore heterogeneous systems is becoming more common, often driven by the software workloads, but the tooling to help optimize the processors, interconnect, and memory are disjointed. Over the past few years, many tools have emerged that help with the definition and implementation of a single processor, optimized for a given set of software. ... » read more

Week In Review: Automotive, Security, Pervasive Computing
By Liz Allan - 23 Jun, 2023 - Comments: 0

Stellantis and Foxconn formed a 50/50 joint venture called SiliconAuto, to be headquartered in the Netherlands. The goal is to close the gap between supply and demand for chips used in computer-controlled features and modules, especially for electric vehicles (EVs). The U.S. Department of Justice created a National Security Cyber Section within its National Security Division to increase the ... » read more

The Uncertainties Of RISC-V Compliance
By Ann Mutschler - 22 Jun, 2023 - Comments: 0

How far can a RISC-V design be pushed and still be compliant? The answer isn't always black-and-white because the RISC-V concept is very different from previous open-source projects. But as interest and activity in RISC-V continues to grow, constructive discussions are taking place to address some of the challenges of designing with an open-standard ISA. “The RISC-V standard is somethin... » read more

Verification And Test Of Safety And Security
By Brian Bailey - 22 Jun, 2023 - Comments: 0

Functional verification can cost as much as design, but new capabilities are piling onto an already stressed verification methodology, leaving solutions fragmented and incomplete. In a perfect world, a semiconductor device would be verified to operate according to its complete specification, and continue to operate correctly over the course of its useful life. The reality, however, is this i... » read more

Better Choreography Required For Complex Chips
By Karen Heyman - 22 Jun, 2023 - Comments: 0

The rapidly growing number of features and options in chip design are forcing engineering teams to ratchet up their planning around who does what, when it gets done, and how various components will interact. In effect, more elements in the design flow need to be choreographed much more precisely. Some steps have to shift further left, while others need to be considered earlier in the plannin... » read more

Shift Left With Calibre To Optimize IC Design Flow Productivity, Design Quality, And Time To Market
By Siemens EDA - 21 Jun, 2023 - Comments: 0

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full sign-off verification. However, waiting until sign-off verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware... » read more

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