Packetized Scan Test


Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, Mobility The U.S. space agency NASA entered a $57.2 million contract with ICON to develop technology to build roads on the moon. ICON, a Texas-based 3D printing construction company, has been working with NASA and the U.S. Air Force on construction technologies that can use local materials to build infrastructure on Mars. NASA is working on advanced 3D printing construction systems... » read more

Peeling The Onion Of An Automotive IC Digital Twin


This paper defines the modern digital twin in the context of the automotive industry and as it applies to the ICs being deployed therein. Additionally, it surveys the implications arising from the need to use digital twins to connect the virtual and physical worlds for semiconductor suppliers delivering the next generation of automotive capabilities. Why should I care about digital twins? T... » read more

Cybersecurity Risks Of Automotive OTA


Modern vehicles increasingly resemble supercomputers on wheels, with many electronic control units (ECUs) networked together as increasingly sophisticated software is installed and updated. Similar to smartphones, vehicle OEMs will contact vehicle owners remotely about operating system updates that add new features and/or fixes, as well as software bugs and vulnerabilities. But all of this h... » read more

Why Better Mapping Technology Is Critical To Autonomous Vehicles


Autonomous cars find the way to their destination using a number of critical technologies, including some version of a global position system and a central brain to interpret that and other data. But many of those technologies are not reliable or accurate enough today, and may not be for years to come. There are numerous reports of vehicles missing their stop, or trucks being guided into all... » read more

Blog Review: Nov. 30


Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows


Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

An Organic Package Designer’s Guide To Transitioning To FOWLP And 2.5D Design


The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs. In most cases system and packaging teams do not have to abandon their existing tool set to support these designs. In fact, the packaging design tool set can offer additi... » read more

Blog Review: Nov. 23


Siemens EDA's Harry Foster looks at multiple data points to get a sense of effort spent in FPGA verification and increasing demand for FPGA verification engineers. Synopsys' Rimpy Chugh, Himanshu Kathuria, and Rohit Kumar Ohlayan argue that the quality of the design and testbench code is critical to a project’s success and that linting offers a comprehensive checking process for teams to s... » read more

Mastering FOWLP And 2.5D Design Is Easier Than You Think


IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, pa... » read more

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