tag: metrology

Better Inspection, Higher Yield
By Bryon Moyer - 08 Sep, 2020 - Comments: 0

Wafers can be inspected for large, obvious defects, or for small, subtle ones. The former is referred to as macro-inspection, while the latter is micro-inspection. These processes use different machines with different capital and operating costs, and they might look like competing approaches with different economic returns. In fact, they are complementary tactics that can be balanced within an ... » read more

Case Study – Socket Metrology
By CyberOptics - 11 Aug, 2020 - Comments: 0

From hours to seconds, the SQ3000 CMM optimized our customer’s backend inspection and socket metrology cutting cost and increasing yields for their high-volume manufacturing.Our customer was leveraging a Coordinate Measurement Machine (CMM) to handle the intricate measurements required for their socket metrology, semiconductor jigs and mobile phone sensors. Click here to continue reading. » read more

Speeding Up The R&D Metrology Process
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times. The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generati... » read more

SEMI 3D1 – Terminology For Through Silicon via Geometrical Metrology
By SEMI - 17 Jun, 2020 - Comments: 0

Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV). Click here to read more, fee for access. » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

What’s Next With AI In Fabs?
By Mark LaPedus - 22 Apr, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. Part one ... » read more

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

The Convergence Of Advanced Packaging And SMT
By Subodh Kulkarni - 07 Apr, 2020 - Comments: 0

One statement is almost always true in the electronics industry: smaller is better. The relentless demand for electronic systems that pack more computing power and functionality into less space has driven the development of new processes and designs since the invention of the integrated circuit. In recent years that drive has taken a new direction, literally, as manufacturers have discovered th... » read more

Case Study – Semiconductor Auto Multi Sensor
By CyberOptics - 06 Apr, 2020 - Comments: 0

CyberOptics’ WaferSense sensor, Auto Multi Sensor (AMS), combines an Auto Leveling Sensor (ALS), Auto Vibration Sensor (AVS), and a humidity sensor in a thin, light, all-in-one multi sensor. The ALS and AVS have well-established records of success for their ease-of-use, robust performance and convenient form factor. The addition of the humidity sensing (to tilt and vibration) in the AMS lets ... » read more

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