Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)


A new technical paper titled "Memory DisOrder: Memory Re-orderings as a Timerless Side-channel" was published by researchers at University of Washington, Duke University, UC Santa Cruz, Raytheon and Microsoft Research. Abstract "To improve efficiency, nearly all parallel processing units (CPUs and GPUs) implement relaxed memory models in which memory operations may be re-ordered, i.e., ex... » read more

Chip Industry Technical Paper Roundup: Sept 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=477 /] Find more semiconductor research papers here. » read more

Analog Plus 3D Optics to Accelerate AI inference and Combinatorial Optimization (Microsoft, Cambridge)


A new technical paper titled "Analog optical computer for AI inference and combinatorial optimization" was published by researchers at Microsoft Research, Barclays and University of Cambridge. Abstract "Artificial intelligence (AI) and combinatorial optimization drive applications across science and industry, but their increasing energy demands challenge the sustainability of digital comput... » read more

DL Compiler Framework For More Efficient Inter-Core Connected AI Chips (UIUC, Microsoft)


A new technical paper titled "Elk: Exploring the Efficiency of Inter-Core Connected AI Chips with Deep Learning Compiler Techniques" was published by researchers at the University of Illinois Urbana-Champaign (UIUC) and Microsoft Research. Abstract "To meet the increasing demand of deep learning (DL) models, AI chips are employing both off-chip memory (e.g., HBM) and highbandwidth low-laten... » read more

Research Bits: April 22


PIC heterogeneous integration Researchers from Hewlett Packard Labs, Indian Institutes of Technology Madras, Microsoft Research, and University of Michigan built an AI acceleration platform based on heterogeneously integrated photonic ICs. The PIC combines silicon photonics along with III-V compound semiconductors that functionally integrate lasers and optical amplifiers to reduce optical l... » read more

Chip Industry Technical Paper Roundup: Mar. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=415 /] Find more semiconductor research papers here. » read more

Energy-Efficient Scalable Silicon Photonic Platform For AI Accelerator HW


A new technical paper titled "Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators" was published by researchers at HP Labs, IIT Madras, Microsoft Research and University of Michigan. Abstract "The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workload... » read more

Chip Industry Technical Paper Roundup: Feb. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=405 /] Find all technical papers here. Also find more research and latest news here. » read more

Wafer-Scale Computing for LLMs (U. of Edinburgh, Microsoft)


A new technical paper titled "WaferLLM: A Wafer-Scale LLM Inference System" was published by researchers at University of Edinburgh and Microsoft Research. Abstract "Emerging AI accelerators increasingly adopt wafer-scale manufacturing technologies, integrating hundreds of thousands of AI cores in a mesh-based architecture with large distributed on-chip memory (tens of GB in total) and ultr... » read more

← Older posts