tag: modeling

Improving Performance And Lowering Power In Automotive
By Ann Mutschler - 20 Jul, 2023 - Comments: 0

Automotive OEMs are boosting their investments across the semiconductor ecosystem as stepping stones toward electrification and autonomy, and they are starting to encounter some of the same issues chipmakers have been wrestling with at advanced nodes — massive compute performance, thermal and power issues, reliability over extended lifetimes, and a highly diverse and geographically distribute... » read more

Balancing AI And Engineering Expertise In The Fab
By Laura Peters - 28 Jun, 2023 - Comments: 1

Modeling and simulation are playing increasingly critical roles in chip development due to tighter process specs, shrinking process windows, and fierce competition to bring technologies to market first. Before a new device makes it to high-volume manufacturing, there are countless engineering hours spent on developing the lithography, etching, deposition, CMP, and many other processes, at hi... » read more

True 3D-IC Problems
By Brian Bailey - 27 Apr, 2023 - Comments: 0

Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Impact Of Increased IC Performance On Memory
By Ed Sperling - 30 Mar, 2023 - Comments: 0

Increasing performance in advanced semiconductors is becoming more difficult as chips become more complex. There are more physical effects to contend with, different use cases, and challenges in making memory go faster. In addition, aging effects that once were ignored are now becoming critical concerns. Steven Woo, fellow and distinguished inventor at Rambus, talks about different factors that... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Design And Verification Methodologies Breaking Down
By Brian Bailey - 12 Jan, 2023 - Comments: 0

Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

EVs Raise Energy, Power, And Thermal IC Design Challenges
By Ann Mutschler - 06 Oct, 2022 - Comments: 0

The transition to electric vehicles is putting pressure on power grids to produce more energy and on vehicles to use that energy much more efficiently, creating a gargantuan set of challenges that will affect every segment of the automotive world, the infrastructure that supports it, and the chips that are required to make all of this work. From a semiconductor standpoint, improvements in th... » read more

Verification Methodologies Evolve, But Slowly
By Brian Bailey - 29 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

Arm’s Input Qualification Methodology Using PowerPro
By Siemens EDA - 27 Apr, 2022 - Comments: 0

This white paper proposes a new automated input qualification methodology that Arm developed using Siemens EDA’s PowerPro software portfolio that performs various data integrity checks at the IC design build and prototype stage. This methodology ensures in quicker iterations that input data are high fidelity, leading to a well correlated power numbers. Should multiple iterations be necessary,... » read more

Unintended Coupling Issues Grow
By Brian Bailey - 24 Feb, 2022 - Comments: 0

The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

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