tag: Molybdenum

High-Temperature Processing of Molybdenum Interconnects
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A technical paper titled "Solving the Annealing of Mo Interconnects for Next-Gen Integrated Circuits" was published by researchers at the National University of Singapore, A*STAR, and imec. Abstract "Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated ... » read more

Interconnects: Criteria For Alternative Metal Benchmarking And Selection (Imec, KU Leuven)
By Technical Paper Link - 19 Jun, 2024 - Comments: 0

A technical paper titled “Selecting Alternative Metals for Advanced Interconnects” was published by researchers at imec and KU Leuven. Abstract “Today, interconnect resistance and reliability are key limiters for the performance of advanced CMOS circuits. As transistor scaling is slowing, interconnect scaling has become the main driver for circuit miniaturization, and interconnect lim... » read more

Comparing Thermal Properties In Molybdenum Substrate To Si And Glass For A System-On-Foil Integration (RIT, Lux)
By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “Comparative Analysis of Thermal Properties in Molybdenum Substrate to Silicon and Glass for a System-on-Foil Integration” was published by researchers at Rochester Institute of Technology and Lux Semiconductors. Abstract: "Advanced electronics technology is moving towards smaller footprints and higher computational power. In order to achieve this, advanced packag... » read more

Backside Power Delivery Gears Up For 2nm Devices
By Laura Peters - 26 Feb, 2024 - Comments: 1

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

Etch Processes Push Toward Higher Selectivity, Cost Control
By Laura Peters - 18 May, 2023 - Comments: 0

Plasma etching is perhaps the most essential process in semiconductor manufacturing, and possibly the most complex of all fab operations next to photolithography. Nearly half of all fab steps rely on a plasma, an energetic ionized gas, to do their work. Despite ever-shrinking transistor and memory cells, engineers continue to deliver reliable etch processes. “To sustainably create chips... » read more

Big Changes Ahead In Power Delivery, Materials, And Interconnects
By Laura Peters - 22 Mar, 2023 - Comments: 0

Part one of this forecast looked at evolving transistor architectures and lithography platforms. This report examines revolutions in interconnects and packaging. When it comes to device interconnects, it’s hard to beat copper. Its low resistivity and high reliability have served the industry exceedingly well as both on-chip interconnect and wires between chips. But in logic chips, with int... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

EUV Pellicles Finally Ready
By Mark LaPedus - 22 Mar, 2021 - Comments: 0

After a period of delays, EUV pellicles are emerging and becoming a requirement in high-volume production of critical chips. At the same time, the pellicle landscape for extreme ultraviolet (EUV) lithography is changing. ASML, the sole supplier of EUV pellicles, is transferring the assembly and distribution of these products to Mitsui. Others are also developing pellicles for EUV, a next-gen... » read more

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