Model Variation And Its Impact On Cell Characterization

By Umang Doshi - 05 Nov, 2020 - Comments: 0

EDA (Electronic Design Automation) cell characterization tools have been used extensively to generate models for timing, power and noise at a rapidly growing number of process corners. Today, model variation has become a critical component of cell characterization. Variation can impact circuit timing due to process, voltage, and temperature changes and can lead to timing violations, resulting i... » read more

Machine Learning Enabled High-Sigma Verification Of Memory Designs

By Nebabie Kebebew - 15 Oct, 2020 - Comments: 0

Emerging applications and the big data explosion have made memory IPs ubiquitous in modern-day electronics. Specifically, the demand for memories with low-die area, low voltage, high capacity, and high performance is rising for use by data center and cloud computing servers. This is essential to serve the exponentially growing connectivity boom and the latest emerging 5G based systems, includin... » read more

Monte Carlo Analysis Using Synopsys Custom Design Platform

By Synopsys - 23 Sep, 2020 - Comments: 0

In this 5th video of the series, Kai Wang, Director of Engineering at Synopsys, explains the need of Monte Carlo to improve yield, and how designers use advanced features like variation scoping and sigma amplification to avoid costly MC simulations. Click here to watch this video white paper. » read more

Problems And Solutions In Analog Design

By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

Timing Library LVF Validation For Production Design Flows

By WeiLii Tan - 27 Feb, 2020 - Comments: 3

Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

Automotive IC Design Demands Next-Generation High-Sigma Verification

By Jeff Dyck - 07 Feb, 2019 - Comments: 0

By Jeff Dyck High-sigma analysis is required for verifying replicated components, like memory blocks and standard cells, and for demonstrating mission-critical reliability for automotive and medical applications. It is not feasible to verify to high-sigma using brute-force Monte Carlo, as this requires 10s of millions of simulations to reach 5-sigma and billions in order to reach 6-sigma. S... » read more

Process Variation And Aging

By Ann Mutschler - 17 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; and Naseer Khan, vice president of sales at M... » read more

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments

By Fraunhofer IIS/EAS - 07 Nov, 2018 - Comments: 0

On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavio... » read more

Practical Methods To Overcome The Challenges Of 3D Logic Design

By Benjamin Vincent - 25 Jun, 2018 - Comments: 0

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other. The Challenge: How can we shrink logic devices? Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?