tag: Moore’s Law

Get Ready For In-Mold Electronics
By Jeff Dorsch - 11 Sep, 2017 - Comments: 1

Imagine inserting the electronics into a product without using a printed circuit board, a module, or even a system-in-package. That's the promise of in-mold electronics (IME), a technology that has been around for years, but which is just beginning to see wider adoption. The technology is related to conductive inks and transparent conductive films. The IME manufacturing process is said to pr... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 24 Aug, 2017 - Comments: 0

Aart de Geus, chairman and co-CEO of [getentity id="22035" e_name="Synopsys"], sat down with Semiconductor Engineering to discuss machine learning and big data, the race toward autonomous vehicles, systems vs. chips, software vs. hardware, and the future of EDA. What follows are excerpts of that conversation. SE: The whole tech world is buzzing over data and how it gets used in areas such as... » read more

The 200mm Equipment Scramble
By Ed Sperling - 23 Aug, 2017 - Comments: 0

An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available, and not all of the new or expanding 200mm fabs can afford to pay the premium for refurbished or new equipment. This may sound like a straightforward supply and demand issue, but behind t... » read more

Rethinking Computing Fundamentals
By Ed Sperling - 10 Aug, 2017 - Comments: 0

New compute architectures—not just new chips—are becoming a common theme in Silicon Valley these days. The whole semiconductor industry is racing to find the fastest, cheapest, lowest-power approach to processing. The drivers of this shift are well documented. Moore's Law is slowing down, in part because it's becoming more difficult to route signals across an SoC at the latest process no... » read more

Is Design Innovation Slowing?
By Brian Bailey - 10 Aug, 2017 - Comments: 0

Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

IP Challenges Ahead
By Brian Bailey - 10 Aug, 2017 - Comments: 0

The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

What Does An IoT Chip Look Like?
By Ed Sperling - 19 Jul, 2017 - Comments: 4

By Ed Sperling and Jeff Dorsch Internet of Things chip design sounds like a simple topic on the face of it. Look deeper, though, and it becomes clear there is no single IoT, and certainly no type of chip that will work across the ever-expanding number of applications and markets that collectively make up the IoT. Included under this umbrella term are sensors, various types of processors, ... » read more

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law
By John Eble - 13 Jul, 2017 - Comments: 0

Moore’s Law, the observation that the available transistors in an integrated circuit doubles every two years, has driven the semiconductor and IT industries to unparalleled growth over the last 50+ years. These transistors have been used in CPUs to increase the number of parallel execution units and instruction fetches, expand the levels of on-chip cache (and overall capacity), support spe... » read more

Inside Chip R&D
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss R&D challenges, EUV and other topics with Luc Van den hove, president and chief executive of Imec, an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Clearly, Moore’s Law is slowing down. The traditional process cadence is extending from 2 years to roughly 2.5 to 3 years. Yet, R&D is not slowing down, right? ... » read more

Going Vertical?
By Debra Vogler - 15 Jun, 2017 - Comments: 0

The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

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