Frenzy At 10/7nm

Focus is on cutting costs across the board, and it turns out there is still quite a bit to cut.


The number of chipmakers rushing to 10/7nm is rising, despite a slowdown in Moore’s Law scaling and the increased difficulty and cost of developing chips at the most advanced nodes.

How long this trend continues remains to be seen. It’s likely that 7/5nm will require new manufacturing equipment, tools, materials and transistor structures. Beyond that, there is no industry-accepted roadmap, making the future far murkier than at past nodes. But at least for now, more companies are betting big on  10/7nm than anyone would have anticipated several years ago—and that is not a decision anyone is taking lightly.

“Before 28nm, companies may have done less business analysis to determine if the business case for making a node-over-node jump made sense,” said Michael White, director of product marketing for Calibre Physical Verification at Mentor, a Siemens Business. “Most everyone just assumed they had to competitively jump, and upon finishing project one at node n, would then initiate project two at node n-1. The node-over-node jump ordered layout shrinks, then added more devices, IP and memory — done. Sub-28nm, the level of design/validation difficulty of jumping node-over-node is much harder.”

It’s also much more expensive, and a wrong move can have a lasting impact on a business.

“Wafer costs and mask costs are higher, and larger IP teams are needed,” White said. “You need to be far more careful to validate that there is a sufficient market for your chips to close your business case justifying the development. Also, you need to ensure that you have the financial and personnel resources to execute what will be a bigger project than needed at the prior node. This isn’t to say there are far fewer companies making the jump, because we have more than 100 companies using Calibre for sign-off DRC/DP/MP sub-28nm. This is many, many more than you would expect if you accept the blogosphere’s assertion that only the large companies will do finFET nodes. But companies are being more thoughtful before jumping into an increasingly deeper pool.”

That view is echoed across the semiconductor industry. The push to 10/7nm has put new emphasis on the business aspects of technology.

“Process nodes such as 10nm and 7nm are chosen not necessarily to achieve higher performance, but to support high-volume production, low turnaround time and profitable business,” said Tobias Bjerregaard, CEO of Teklatech. “Stable production flows that address technological challenges of the most advanced nodes using fully automated production flows are the center of discussions today.”

None of this is being done in a vacuum, of course. Big chipmakers are experimenting with a number of options, including heterogeneous integration of multiple chips in a package, different memories, and entirely new architectures. But device scaling remains a key part of that picture, at least for now.

“If you make chips, the fabrication is a very important part of it, and it is what has really defined Moore’s Law in the past,” Bjerregaard said. “But making a chip involves everything from getting the idea, to designing the circuits, to production. It makes it a little less sexy, but it is a good thing because it used to be all about performance with Intel and AMD fighting each other over megahertz of processors and processor power and so on. It is now becoming a more stable industry, and we need to look at stable production and profitability.”

What’s surprising, though, is the diversity of companies pushing to the next node. Relatively new technologies, such as artificial intelligence and cloud computing, are heavily leveraging the most advanced nodes. Neither of these markets was  on the radar a couple of process nodes ago. Even carmakers, which traditionally have trailed Moore’s Law by at least several nodes, will utilize the latest nodes for AI developed for assisted- and autonomous driving.

“Everybody who wants to do AI needs the performance, power and form factor of 7nm and below,” said Christen Decoin, product management director in Cadence‘s Digital & Signoff Group. “Everybody who wants to play there has to have something there, and that’s big companies and small companies. A second driver is server chips, and everything that’s linked to the cloud. You see companies like Google and Amazon are putting more and more resources in the cloud, and there are more and more things happening in the cloud. If you want to be in a server chip, you have to be at 7nm. Third, in the automotive sector it’s not the usual power MOS stuff. It’s more MCUs, infotainment. There is a huge market. Between these three verticals, you have 20 to 40 customers looking at 7nm, which is remarkable. We’ve not seen this in the industry in the last 20 years.”

Fig. 1: Google’s AI chip/board. Source: Google

Lisa Minwell, eSilicon‘s director of IP marketing, agrees. “It’s still the typical big guys who can afford to do this. But we’re also seeing a startup in networking moving to 7nm. For them, the biggest driving factor is having 112 gigabit-per-second SerDes available. The qualification cycle for larger IP is harder. Validating in silicon is not as easy.”

What’s different
At 10/7nm, processes are much more complex. As a result, there are more rules and constraints, and an enormous amount of innovation being done on design methodologies and tools.

“We are not necessarily scaling in the same way, on the same schedule, with the same benefits as the last 50 years, or whatever time line you want to use,” said Tom Ferry, vice president in the Silicon Engineering Group at Synopsys. “And the innovation is certainly different. The innovation before was about doing planar CMOS. We were scaling dimensions sort of equally, and it would benefit power and density and cost and performance sort of at a similar rate. Now things are much more complicated and you can’t just scale dimension and get all of these benefits because of the geometries we are working at. It doesn’t work that way. It’s not linear.”

Beyond up-front design, innovation is happening in process development, transistor device development, and in lithography strategies.

“Also on the back end, in yield ramp there’s quite a bit of innovation there, Ferry noted. “Of course, all of this innovation comes from problems, so process device litho options are all about the scaling and the physics and getting around all those problems. The yield ramp is sort of an outgrowth of that because things are just so complicated that getting a product to production yield is much harder than it was so there are innovations across-the-board there.”

Ferry added that there is more focus by the foundries on optimizing existing nodes, such as 28nm, 20nm, 16nm, and 14nm for specific applications, including auto RF and low-power IoT. “There’s also a lot more attention and innovation in reducing variability. Because of all the physics, variability is a huge problem. We don’t have the margins that we had before, and instead of being able to add the margins we really have to work at reducing variability—and that is almost at the atomic level. People are analyzing that.”

Synopsys is working on a design technology co-optimization flow, which is all about the effects of a new process on the end design and the design goal. “Design a transistor and carry it through standard cell design and place-and-route of a processor core and see how well that transistor works in that environment from the view of power, performance, area and yield. Things are so complex and people have so many options at their disposal for how to design a transistor or the process flow, or the litho strategy, that they need to sort through all of these options. They can’t do it just based on experience and prior knowledge. The effect for us is there is a lot more simulation and TCAD and lithography much much earlier, and the standard cell designers and the chip designers are getting involved in evaluating those options much much sooner than before.”

New math
Beneath this frenzy of development around new tools and flows is an overriding concern about the rising costs associated with scaling.

“The cost per transistor has not been going down since 28nm,” said Teklatech’s Bjerregaard. “At the same time there’s a lot of competition and it’s all about profitability. The consolidation in the industry is due partly to the fact that in order to compete you need to have chips with very high volumes — at least 100 million copies — in these new manufacturing technologies. The focus is on getting production, and getting yield, and getting that 7% profitability up to 8% profitability. It’s just a different game than back in the ’90s and the ’00s, where it was about performance.”

He said that in the mobile market, the battle is over tweaking the last few percent out of the fabrication technologies. “What you can see at those big companies is that also for the engineers working day to day with layout, it’s not only based on technology merits that they choose EDA technologies. It’s a business decision. It’s a strategic decision. And you don’t get around the question of how an EDA technology turns into dollars on the bottom line. If you have a huge design department with hundreds of people, if one tool breaks and those hundreds of people are sitting around, it’s very expensive.”

Fig. 2: 7nm transistors packed below 30nm fin pitch. Source: IBM

There is also more work underway to eliminate inefficiency in the production flow. This requires a whole new level of efficiency across the supply chain.

“If you want to tighten it, and make it profitable, you have to be very stringent in the whole process,” Bjerregaard said. “This is especially true for the top-tier semiconductor companies because they all have access to the same fabrications technologies. They all have access to the same EDA tools and they more or less have access to the same architectures. So where do they really make a difference? That’s where production stability comes into the discussion, because that’s an art form and you can’t just add that by buying a flow. You have to have it in your culture. You have to have it in the way you set up your production. Everything has to go in there—the way you double check everything, how you quantify and qualify success, among other things.”

Along the same lines, Cadence’s Decoin points to changing tactics of the foundries. “The foundries want to work with fewer players because this node is much more complex to put in place,” he said. “To enable the EDA vendor, it’s a lot of investment from their part, so they have to limit the number of partners.”

Complex industry dynamics
There is no simple formula for why companies are rushing to 10/7nm. In an industry as dynamic as the semiconductor industry, it’s difficult to characterize every company and every design situation.

“There are a lot of considerations for migrating down to the next nodes,” said Jeff Galloway, CTO of Silicon Creations. “In the past if you migrated down, you would save costs on transistors. And from 65nm to 40nm, and down to 28nm and 16nm, that was reality. Moving from 16nm to 7nm is a bit murkier. So really what you’re looking at is IP availability.”

Still, when it comes to the 10/7nm node, it appears there is more activity than might have been predicted based on the usual historical trend. With each new technology node, the risks are very high, there are yield issues, reliability issues, and that only a handful of customers would go to the node.

“The feeling was that at 7nm, the price was going to be so high that [the historical trend] would be even more accentuated, but right now it’s not a handful of customers looking at 10 and 7nm,” said Decoin. “It’s more than 20.”

That has put new focus on cost cutting at 10/7nm and beyond, and more understanding about exactly what that entails.

“The big semiconductor companies will reach for any and every tool they can to enhance their understanding of yield ramp and node development,” said Matt Knowles, product marketing manager for silicon learning products at Mentor. “They’ve generated all this data but never had the financial justification to really analyze it and look at it. The big change is that now there is a financial justification to squeezing every little bit they can. We are reaching a lot of fundamental limits, and the fact is there is still some value to squeeze out of what we have from these analytics and analysis techniques. It’s not just the techniques themselves. It’s the cross-correlation.”

There is still room for price improvement at 10/7nm, and maybe well beyond that.

“It’s about stable production design flows that create chips in a stable and professional way, but that doesn’t mean that there’s no money in it and there’s no opportunities and challenges for the EDA industry or startups,” said Bjerregaard. “It just means we put the focus elsewhere. Often it’s someplace that nobody thought of because it’s not something that is talked about all the time. It’s more about, ‘Wow, we can actually save millions of dollars just by doing things in ‘this’ way in this corner of the design flow.”

And when there is no more to squeeze out of existing processes and tools, there are other options under development.

“Considering the yield vs. performance/power vs. innovation equation, everybody is looking at the next node, and there is a lot happening from the ‘More Than Moore’ perspective—silicon photonics, 3D-IC integration, package-on-die, and so on,” said Decoin. “After 7nm there will be 5nm and 3nm, and even if fewer companies go there, there will still be innovation. It’s just that it won’t be a shrink of transistor size anymore.”

Fig. 3: 3D stacked test chips. Source: Imec

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