Today IoT Is Cool, Tomorrow IoT Can Change Mankind

By Linh Hong - 03 Sep, 2015 - Comments: 0

Who today doesn’t think IoT is cool? And, why not? We’re in an era where everything is connected to everything else in a six degrees of separation-like scenario for our electronics devices. Automatic washing machines and domestic refrigerators were cool to our grandparents because they enabled them to have more time for other pursuits. IoT is cool today for the same reason. Smart homes,... » read more

Software Driving More Hardware Designs

By Ed Sperling - 27 Aug, 2015 - Comments: 2

The influence of software engineers is growing inside of chip and systems companies, reversing a decades-old trend of matching the software to the fastest or most power-efficient hardware and raising as-yet unanswered questions about what will change in SoC design. The shift is particularly evident in chips developed for high-volume markets such as mobile phones and tablets. It's also happen... » read more

Electronics Butterfly Effect

By Brian Bailey - 27 Aug, 2015 - Comments: 1

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency

By Kurt Shuler - 27 Aug, 2015 - Comments: 0

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

Shrinking R&D Pool

By Ed Sperling - 20 Aug, 2015 - Comments: 2

The rule of thumb in business is that consolidation in a maturing industry improves the health of the surviving companies. In most market sectors that's true. In the semiconductor industry, that formula doesn't work. The reason is due to what might well be called foundational economics. While it's possible to reduce costs in making chips for years to come, at some point the basic building bl... » read more

Advanced IC Packaging Biz Heats Up

By Mark LaPedus - 20 Aug, 2015 - Comments: 0

After a number of false starts and lackluster adoption, the advanced IC packaging market is finally heating up. On one front, for example, a new wave of chips based on advanced [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] stacked-die is entering the market. And on another front, the momentum is building for new and advanced 2D packages, such as embedded package-on-package (PoP... » read more

Interconnect Challenges Grow

By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

What Works After 7nm?

By Mark LaPedus - 20 Aug, 2015 - Comments: 3

An Steegen, senior vice president of process technology at [getentity id="22217" e_name="Imec"], the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm. SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right? Steegen:... » read more

Moving Electrons Is Getting Harder

By Ed Sperling - 13 Aug, 2015 - Comments: 1

Numerous executives across the ecosystem—from EDA and equipment companies to foundries—recently have stated that Moore's Law has at least 10 more years of life. This is interesting math, considering the semiconductor industry is now working on 10nm, with chips expected to roll out next year. So given that Moore's Law is on a two-year cadence of doubling the number of transistors every 24... » read more

Executive Insight: Aart de Geus

By Ed Sperling - 10 Aug, 2015 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?