What’s Different At 16/14nm?

By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Executive Insight: Jack Harding

By Ed Sperling - 28 May, 2015 - Comments: 0

SE: What's changed over the past 12 months? Harding: My starting point these days is around consolidation. At last count there were about 85 companies in the semiconductor industry. My bet is that at this time next year there will be about 70. The size of deal will not matter. Nothing will be too big. The strategic question is whether you're playing musical chairs and when the music stops, ... » read more

How Semiconductor IP Became Critical To SoC Design

By Kilopass - 07 May, 2015 - Comments: 0

By Mark Templeton In 1991, I had the good fortune to be a member of the founding team of Artisan Components. We started the company believing that demand was about to appear for semiconductor intellectual property. We had a few data points. We knew that before a company could start a new chip project, they first had to design and verify all kinds of generic building blocks – things like ... » read more

Moore’s Law At 50

By Ed Sperling - 23 Apr, 2015 - Comments: 0

Moore's Law turned 50 this week…but not because of Gordon Moore. He observed that the number of transistors crammed onto a piece of silicon was doubling every 18 to 24 months and predicted that would continue to be the case. He was right, but it took many thousands of engineers who created methodologies and tools to automate the design and equipment to manufacture complex chips to make that o... » read more

What EDA’s Big 3 Think Now

By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Pressure Builds To Revamp The Design Flow

By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Less Moore Means More Intelligence

By Brian Bailey - 23 Apr, 2015 - Comments: 3

It would seem as if the entire industry is flooding the forums with articles about [getkc id="74" comment="Moore's Law"], as it reaches its 50th birthday (April 19th) and that this represents the longest and most important exponential in the history of man. The numbers and that impact are everywhere and I do not intend to repeat them. There are lots of articles talking about when Moore’s law ... » read more

Blog Review: April 22

By Jesse Allen - 22 Apr, 2015 - Comments: 0

DARPA thinks machine-brain interfaces are poised to become an industry-changing technology. Rambus' David G. Stork brings us emerging developments in the field from the Neural Engineering Boot Camp. If you live in an area that doesn't get quite enough sun for solar panels, how about a smart window that harvests energy from wind and rain? In this week's top five picks, Ansys' Justin Nescott a... » read more

New Patterning Paradigm?

By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or br... » read more

50 Years Of Moore’s Law

By Bettina Weiss - 16 Apr, 2015 - Comments: 0

The Industry at 50 This month marks the 50th anniversary of Moore’s Law, an amazing milestone for the semiconductor industry. Looking back through our industry’s history, we must marvel at the speed, growth, technical sophistication and transformative changes computer chips have made over the past few decades. None of this would have been possible without semiconductor equipment and materi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?