What’s Different At 16/14nm?

FinFET-based design is expensive and difficult, with parts of road map still under construction, but progress is being made.


Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it’s getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases.

There is no question that finFET offer big advantages to companies working on high-volume ASICs and SoC, and the option of higher density for an FPGA. There are significant performance advantages to be had for a couple reasons. First, there are more transistors to work with and more real estate for optimizing throughput, including space for more memories closer to various processors on a chip and more options for wider wires where necessary. And second, clock speeds can increased due to the fact that static leakage is well under control for the first time in five process nodes, thereby reducing the amount of heat.

From a purely technical standpoint, finFETs are required to advance down the ITRS roadmap, and there is plenty of documentation and silicon to show that the technology works as promised. A survey by Synopsys shows more than 200 finFET-based tapeouts so far. The three-sides of the fin, including two on each side and one at the top, allow current to be controlled much more effectively at the gate, so when a device is turned off the battery no longer continues to drain. This is a big deal, and it took nearly two decades to perfect this technology.

But it’s also a big change, and there’s a price to pay for these kinds of shifts, at least in the short term. Lithography, EDA tools, and process technology are out of sync at 16/14nm. Well-documented delays in EUV lithography, increases in dynamic power density, and simply more of everything on a piece of silicon have boosted the cost of developing chips at 16/14nm.

Karim Arabi, vice president of engineering at Qualcomm, called “a huge megatrend.” While performance and scaling are accelerating, cost per transistor is rising. “The cost aspect of Moore’s Law is not scaling beyond 28nm. This will improve somewhat at 10nm, but it will still be a concern. EDA and architectural innovation are still required.”

Linear or exponential complexity?
Regardless of the target market for a finFET design, the reality is there is more of everything on chips at the latest process node. Just figuring out how all of those pieces will work together has put a strain on all existing tools and methodologies.

“We live under the curse of Moore’s Law,” said Kuang-Kuo Lin, director of foundry design enablement at Samsung. “There are billions of devices in a chip. The physics and fundamentals are the same, but there are more of everything and they have to communicate. All things interact with each other.”

Even visualizing these kinds of interactions requires 3D models. There is much more data to process, and EDA vendors are in an all-out race to update their tools and create ways to blend existing with new tools, particularly for place and route, RC extraction, mixed-signal simulation, and emulation for everything from power analysis to software prototyping and system-level verification.

This has created problems from the architectural modeling all the way through to verification and inspection of silicon. There is so much data that has to be processed that data mining is essential even to understand what’s changed. Double patterning has created a massive amount of data by itself, a problem that will get increasingly worse at each new node, with triple or quadruple patterning at 10nm and octuple patterning at 7nm. Even if EUV replaces immersion lithography at 7nm, it will require double patterning for much more complex circuitry.

“The block sizes are bigger,” said Swami Venkat, senior director of marketing for the Galaxy Design Platform at Synopsys. “That affects run-time performance, capacity and memory. The issue is how fast you can run all of this, explore options, and improve turnaround time. In addition, because of lower voltages, variations can be very significant.”

Multi-patterning only makes things worse. But even double patterned masks can be misaligned or shift, which can increase capacitance. That, in turn, has to be accounted for in the design process.

“No one wants to give up accuracy or time to market,” said Carey Robertson, product marketing director at Mentor Graphics. “But to achieve that you now need different techniques for middle end of line and back end of line.”

Parasitic extraction is particularly thorny, in part because there are more corners to deal with, Robertson said. Many of those corners are identified in restrictive design rules within foundry flows, but even keeping track of those is difficult because the number of design rules is ballooning. At 10nm, the problem is much worse again, and at 7nm worse yet again.

He’s not alone in seeing that trend, either. Bo Gao, senior design engineering director at Cypress Semiconductor, said parasitics impact timing, area and performance. That frequently doesn’t show up, however, until post-silicon testing. But chipmakers are looking for ways to reduce that testing, he said, because it’s becoming a significant part of the cost of developing a chip and it takes time.

“For the consumer market, if you’re late by one month you’re probably dead on that product,” Gao said. “You can lose a whole year’s revenue as a result.”

The key, he said, is diligence at every step. Shaving 10 minutes off run time may not sound like much, but if that happens for hundreds of iterations of a chip and involves multiple steps, it can have a significant impact on whether a company is successful with a product. “So do you live with extraction that takes less than 24 hours if it could be less than an hour. And do you deal with corners sequentially, or pay more money to kick off multiple corners at once?”

There is no shortage of awareness about these problems among leading-edge chipmakers. At 16/14nm, flows have been collaboratively developed and tested by foundries, EDA companies and chipmakers. But these are leading-edge chipmakers. A key question for tools and equipment companies is how many other chipmakers will follow them into the finFET world. Or will they stay put at 28nm, maybe using fully depleted silicon on insulator (FD-SOI)—or opt to go in a different direction.

Good or bad news?
All of this has created a need for new tools and methodologies, of course. For chipmakers, that costs money. For tools and equipment makers, it’s a risk because there is no guarantee there will be enough demand for finFET-based designs within a given time period. But it’s also a big opportunity if there is continuous buy-in.

“The farther you go down the geometry curve, the bigger the chips, the lower the power,” said Charles Janac, chairman and CEO of Arteris. “But finFETs are not good for analog, so eventually we’re going to have to mix and match dies. At that point, packaging becomes king.”

Janac, like many others in the industry, believes the future will be a combination of process technologies within a single package, whether it’s 2.5D, 3D, or some variation in between. “This is not just an EDA problem,” he said. “It’s also about the architecture of the IP and how it’s implemented, and you need to be able to run those kinds of analyses on IP. At 40nm, people were still doing some of this stuff by hand. At 28nm and 16/14nm, they have run into trouble. The solution is to over-engineer when things get too complex, but that costs more power, more timing slots, and creates a bigger, costlier and slower chip.”

Intel, Cadence, ARM and Mentor Graphics all have been preparing for the move to stacked die, according to top executives at those companies. In fact, Cadence has been pushing system-in-package approaches for a couple decades, dating back to the turn of the millennium when there was concern about the ability of analog and digital to peacefully coexist on the same die. And many in the IP, equipment and packaging world are keeping their fingers crossed that it happens sooner rather than later, because it offers entirely new opportunities for them.

There is much riding in all directions on what comes next, in what volume, and at what process node or nodes. The rush to 16/14nm may be supplanted by 10nm, which is where TSMC has said it will bet a key part of its future. But how many companies move there, and where they go after 10nm is a guessing game. The answer will likely depend on how well 16/14nm designs fare, what problems are encountered along the way, and what new tools are added to simplify the design through manufacturing flow. And so far, there isn’t enough information to make that call.

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