Resurrecting The Semiconductor Industry

By Satish Bagalkotkar - 24 Jul, 2014 - Comments: 0

Every so often the semiconductor industry approaches a wall, and it takes the best minds in the world to figure out whether to go left, right, below, above or through it. As an industry we faced that at 1 micron, and again at 45nm with lithography. Now we are approaching another wall. Complexity has exploded—hardware, software, IP and process technologies—while the entire time-to-market cy... » read more

Executive Insight: Satish Bagalkotkar

By Ed Sperling - 23 Jul, 2014 - Comments: 1

Semiconductor Engineering sat down with Satish Bagalkotkar, president and CEO of design services company Synapse Design to talk about massive shifts in the semiconductor industry and his vision of how these changes will alter the landscape, from chipmakers to design services to what gets built and how it will get used. What follows are excerpts of that interview. SE: What worries you most? ... » read more

1-on-1 With Intel’s Foundry Chief

By Mark LaPedus - 17 Jul, 2014 - Comments: 1

By Mark LaPedus & Ed Sperling Semiconductor Engineering sat down to discuss foundry trends, IC scaling, chip-packaging and other topics with Sunit Rikhi, vice president of the Technology and Manufacturing Group at Intel and general manager of Intel’s Custom Foundry unit. SE: Where is Intel at in the foundry business today? Rikhi: We started with a very narrow set of customers. Now, we... » read more

What Happened To 450mm?

By The SE Staff - 17 Jul, 2014 - Comments: 1

By Mark LaPedus, Ed Sperling & Katherine Derbyshire There was a time not very long ago—one process node, in fact—when the economic momentum of Moore’s Law seemed unstoppable with a combination of extreme ultraviolet lithography, larger wafer sizes and a variety of new materials. Shrinking feature sizes is still technically possible, but certainly not with the same promised economic benef... » read more

All Roads Point Up…But When?

By Ed Sperling - 17 Jul, 2014 - Comments: 0

One of the clear messages at Semicon West this month was that stacked die are coming soon. The only question is how soon. This isn’t so simple to answer. It depends on a lot of factors, and for most of them there aren’t any clear answers. First of all, no one is certain what the cost equation will look like at 14/16nm, particularly once the process technology becomes more mature. Ther... » read more

After Moore’s Law: More With Less

By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

Stacked Die Are Coming Soon. Really

By Ed Sperling - 10 Jul, 2014 - Comments: 3

Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more

Semiconductor R&D Crisis Ahead?

By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Without Moore’s Law: EDA

By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Executive Insight: Aart de Geus

By Ed Sperling - 02 Jun, 2014 - Comments: 0

SE: What worries you most? De Geus: Everything I do is with high intensity, and what is of super high intensity right now—and there are challenges and opportunities in it—is that we have the confluence of some very big changes right now happening at the same time. On the technology side, there are multiple intersections. One is the intersection of another 10 years of Moore’s Law—finF... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?