Stacked Die Are Coming Soon. Really


Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more

Semiconductor R&D Crisis Ahead?


Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Without Moore’s Law: EDA


Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Executive Insight: Aart de Geus


SE: What worries you most? De Geus: Everything I do is with high intensity, and what is of super high intensity right now—and there are challenges and opportunities in it—is that we have the confluence of some very big changes right now happening at the same time. On the technology side, there are multiple intersections. One is the intersection of another 10 years of Moore’s Law—finF... » read more

Executive Insight: Hossein Yassaie


SE: What concerns you looking out at the semiconductor industry? Yassaie: There are big changes in the industry over the last two years, such as the verticalization in the mobile space. Every semiconductor company wanted to play in mobile. It was just a fact of life that some of these guys would give up. That was a major change, and it was something we could see coming. Our focus is diverse ... » read more

Tech Talk: The New Cost Per Gate Equation


eSilicon's Javier DeLaCruz talks with Semiconductor Engineering about new types of interposers, why just shrinking features is doomed, and what progress has been made in building 2.5D chips. [youtube vid=akj8r8nNktM] » read more

EDA Races To 7nm, Despite Litho Uncertainties


It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

Beyond Moore’s Law


What do you make of all the different reports coming out of Advanced Lithography 2014 — the end of Moore's Law, continued problems with EUV, directed self-assembly assembly makes progress? An equipment insider, whose judgment I value, came back from the meeting and concluded, "We will see the end of Moore’s Law shrinks in 2020. After that, no one knows!” There is no way a $300B+ business ... » read more

What Are EDA’s Big Three Thinking?


Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult... » read more

Favorite Forecast Fallacies


It’s difficult to make predictions, especially about the future. – An Old Danish Proverb. The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Researc... » read more

← Older posts Newer posts →