EDA Races To 7nm, Despite Litho Uncertainties

The delay with EUV isn’t stopping anyone from pushing ahead on design tools for 7nm.


It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren’t yet clear.

Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power problem that becomes a throughput problem, and there’s an uptime problem with the time between maintenance they are seeing on the equipment now.” Also being carefully considered are the overall economics that retooling would require.

Even so, he said the stance of the foundries is that if EUV comes online with reasonable throughput, they will use it. “At 7nm you still need to do multi-patterning at the lower levels, so that cost doesn’t go away. That’s one of the challenges going forward on Moore’s Law: we can probably build stuff down to 5nm or 3nm, but how much is it going to cost to do it? All of the lithography steps are based on a die-image basis and that’s going to be the majority cost. Even going to 450mm wafers isn’t going to mitigate much at all.”

“Given that EUV doesn’t seem very likely,” Carlson continued, “you are stuck with multi-patterning. That’s something that we’ve known about and have been working on for quite some time. When double-patterning came at 20nm, we already were talking about multi-patterning because they weren’t sure if it was just going to be double-patterning or not. It’s something we’ve been aware of for five or six years.”

From an overall EDA industry perspective, the uncertainty of 7nm lithography is not much of a concern—at least not at the moment.

“Uncertainty with lithography process options means that EDA companies supporting the computational lithography market have to support development of all the feasible options,” noted Gandharv Bhatara, product marketing manager for Calibre manufacturing at Mentor Graphics. “This actually has been true for many nodes, not just 7nm. Remember the uncertainties about alternating PSM at the 40nm node? EDA tool development has for quite some time now been running in parallel with process development.”

As they are integrated flow providers, it is safe to say that all EDA providers are committed to have the tools available for all options under consideration for 7nm – EUV, multi-patterning and DSA.

As with all EDA tools, uncertainty spells opportunity. “We build tools that not only enable the various lithography/patterning techniques, but also allow the industry to optimize both design and manufacturing and make practical decisions/choices along the way.”

To do this, EDA and IP providers work very closely with the semiconductor foundries – and 7nm test chip work has been happening for about a year.

Partnerships with foundry customers throughout the development cycle enable tool development to be ready in time for development tape-outs and production, he explained, which has been the development and business model throughout every shrink cycle, most recently evidenced at the 16nm/14nm and 10nm nodes.

Litho impact on 7nm
Design ground rules and constraints are definitely driven by lithographic capabilities. SADP, LELE(LE) multi-patterning and resolution capabilities, including source wavelength and numerical aperture, all play a role in defining design rules, pitches and constraints, according to Mentor’s Bhatara. “Design is definitely dependent on the process and computation lithography choices made at each process technology node. Hence, changes have to be anticipated and planned for. Furthermore, the dependency of design on lithography is becoming more critical as we move to the 7nm node since the industry is pushing the boundaries of what designs can be patterned. This is also triggering a strong demand for process exploration and design technology co-optimization tools.”

Joanne Itow, managing director of manufacturing at Semico Research, agreed that lithography will make a difference. She observed that Intel is preparing for life with EUV and without it. “They will proceed with whichever option is necessary/available at the time of launch. If EUV is not ready, that certainly makes life more difficult, and expensive.”

The decision to proceed without EUV also will hinge on the market situation. “High performance server and network chips can absorb the additional cost of triple or quadruple patterning, but implementation of 7nm for low-cost mobile consumer applications may see some delays. Consumer products can be updated with new features using the same process technology. There are ways to satisfy the consumers’ needs to upgrade their smartphone every year other than just increasing the processor performance,” she said.

At the same time, Itow doesn’t believe the choice of lithography will be a stopping point. “Designers can proceed without EUV. But the remaining options are more expensive, which means product development and market volumes could be limited.” The real challenge is beyond 5nm.

Bhatara added that uncertainties in patterning strategies and constraints definitely play a significant role in developing the design infrastructure at a particular process technology node, but the design community and EDA tool providers seem to continue to find ways to manage the uncertainty and risk. “The two-to-three year shrink cycle has kept pace. Will 7nm be different? Delays in design infrastructure development are possible at 7nm given the very different options under consideration and the uncertainty of EUV deployment. “

As a result, a lot of iterative co-optimization work is ongoing to start out with initial assumptions that will be updated as technology development progresses.

Part of Mentor Graphics’ focus is to create tools that allow the industry to manage this design technology co-optimization process so that the choice of lithography will not be a stopping point, he concluded.

Technical nuts and bolts
As far as the nuts and bolts of multi-patterning go, Cadence’s Carlson said the question to be answered is what is it that you are going to multi-pattern? What kind of devices? “There are candidate choices there that are being narrowed down and that’s something that the foundries will have to talk about.”

In its custom business, Cadence has people working on the design of the test chips using the company’s custom design tools, which gets more to a productivity question, he said. In a custom design environment, which has to do with going to finFET, “being able to automatically lay out an arrangement of fins with the prescribed spacing so that you meet all of the design rules automatically is something that you can do all that manually or you can have some automation around that. Being able to get the new extraction elements into the tools and be able to pull that real time into the custom design environment – this electrically –aware design—being able to get all of the parasitic information as you go into the simulations. That’s a critical productivity enhancer,” he explained.

“When you choose to make a tradeoff in the design rules to improve the manufacturing or make it easier to route the designs and then change the cell libraries, that causes ripples through a lot of the enablement infrastructure,” he said. “There is a whole bunch of scrambling that goes on, but we’ve kind of operationalized it at this point – we did it at 20, 16, 14, 10 and beginning at 7. It’s not a surprise the types of things that we’re going to have to scramble on – you’ve got to be ready because it’s going to happen. We’re going to have to make changes to tweak and tune in order to bring the best value that that geometry can bring in terms of the density, performance and power.”

At the end of the day, Itow summarized perfectly. She recalled when she joined Semico, the industry was at 350nm moving to 250nm. “Even back then I heard complaints that EDA wasn’t expected to keep up with the move to 90nm and 130nm. They managed to keep up.”

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