tag: Moortec

Defining And Improving AI Performance
By Brian Bailey - 12 Dec, 2019 - Comments: 2

Many companies are developing AI chips, both for training and for inference. Although getting the required functionality is important, many solutions will be judged by their performance characteristics. Performance can be measured in different ways, such as number of inferences per second or per watt. These figures are dependent on a lot of factors, not just the hardware architecture. The optim... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Dec, 2019 - Comments: 0

Cadence signed a deal to buy National Instruments’ AWR business unit for about $160 million in cash, a move that Cadence describes as a way to broaden its market into intelligent system design. AWR’s strength is high-frequency RF design automation tools, particularly in the millimeter wave and microwave spectrums, which are critical for radar and 5G. It also has technology for III-V materia... » read more

Week In Review: IoT, Security, Auto
By Susan Rambo - 06 Dec, 2019 - Comments: 0

Internet of Things SiFive is bringing RISC-V to IoT makers and university developers through the RISC-V-based SiFive Learn Initiative, an open-source learning package that can be used to create a low-cost RISC-V hardware compatible with AWS IoT Core. The development platform SiFive Learn Inventor has a software package and education enablement course. It includes: The programmable SiFive Lear... » read more

Verification Pilgrims Show A Historical Case For DFT
By Lee Vick - 27 Nov, 2019 - Comments: 0

The Mayflower Steps, where the Pilgrims are believed to have embarked on their journey to America, are located in the beautiful Barbican area of Plymouth, a small town in the southwest of England. As the lone American working for Moortec, a British company based in Plymouth, I stood and stared at them this past September. Separated by a few yards of distance but 399 years of history I found my... » read more

The Challenge Of Defining Worst Case
By Brian Bailey - 14 Nov, 2019 - Comments: 0

Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

Finding Hotspots In AI Chips
By Stephen Crosher - 14 Nov, 2019 - Comments: 0

Things are getting far more complicated as we move down to 7nm & 5nm but the tolerances of some of the physical effects that we have been measuring in the past are much tighter than they were at the older nodes. How do we track all that? What we see is that as we descend through the advanced nodes, say from 16nm down to 12nm, 7nm and more recently 5nm, we see that gate density starts to ... » read more

Planning For Failures In Automotive
By Ann Mutschler - 07 Nov, 2019 - Comments: 0

The automotive industry is undergoing some fundamental shifts as it backs away from the traditional siloed approach to one of graceful failure, slowing the evolution to fully autonomy and rethinking how to achieve its goals for a reasonable cost. For traditional automakers, this means borrowing some proven strategies from the electronics world rather than trying to evolve traditional automot... » read more

Monitoring Heat On AI Chips
By Ed Sperling - 11 Oct, 2019 - Comments: 0

Stephen Crosher, CEO of Moortec, talks about monitoring temperature differences on-chip in AI chips and how to make the most of the power that can be delivered to a device and why accuracy is so critical. » read more

Why EV Battery Design Is So Difficult
By Ann Mutschler - 03 Oct, 2019 - Comments: 4

Automotive batteries always have been treated as plug-and-play parts of a vehicle, but that approach no longer works in electric vehicles. In fact, the battery is now a differentiating factor, and it is the heaviest and most expensive component. What used to be a relatively simple component has been replaced by a variety of sensors to measure complex static thermal and aging effects, as well... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

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