Week In Review: Design, Low Power

Cadence buys NI’s AWR unit; FPGA simulation; RISC-V cores; early static analysis-based verification.


Cadence signed a deal to buy National Instruments’ AWR business unit for about $160 million in cash, a move that Cadence describes as a way to broaden its market into intelligent system design. AWR’s strength is high-frequency RF design automation tools, particularly in the millimeter wave and microwave spectrums, which are critical for radar and 5G. It also has technology for III-V material design, which is critical for silicon photonics. Cadence said it expects to fully integrate AWR’s tools with its own design and analysis tools. It also will add about 100 AWR employees as part of the purchase. The move comes as Cadence and NI plan to expand a strategic alliance started last year.

Tools & IP
Aldec expanded its Active-HDL IDE for FPGA design and simulation, adding the ability to compile and simulate SystemVerilog verification constructs to improve use in UVM test environments, and for functional coverage and constrained randomization simulations. Additionally, a 64-bit simulation capability was added by default to selected popular configurations, along with enhancements to Active-HDL’s block diagram and state machine editors.

Imagination unveiled the IMG-A Series, the tenth generation of PowerVR GPUs. It targets multiple markets, from automotive, AIoT, and computing through to DTV/STB/OTT, mobile and server with performance scalability ranging from 1 pixel per clock (PPC) parts for the entry-level market up to 2 TFLOP cores for performance devices, and beyond that to multi-core solutions for cloud applications. Compared to current PowerVR GPUs, the IMG-A Series offers 2.5x the performance, 8x faster machine learning processing and 60% lower power with a smaller footprint, according to the company.

Andes debuted two new families of RISC-V CPU cores. The AndesCore 27-series features the RISC-V Vector instruction extension (RVV) and a re-architected memory subsystem. It supports scalable data sizes, flexible microarchitecture implementations, and is available as 32-bit A27 and 64-bit AX27 tailored for applications running Linux and the 64-bit NX27V which contains a Vector Processing Unit (VPU). The AndesCore 45-series includes a superscalar pipeline and targets high-performance, power-sensitive and real-time embedded systems. It is available in 32-bit A45/D45/N45 and 64-bit AX45/DX45/NX45. The A-prefix supports Linux and scales up to four cores, N-prefix supports RTOS, while D-prefix supports RISC-V packed SIMD/DSP instructions (P-extension draft).  All 45-series cores employ in-order, 8-stage, dual-issue superscalar pipeline, ECC, and single and double precision FPU.

vSync Circuits uncorked vLinter, a tool for static analysis-based verification in early design stages. It can be used to find bugs due to bad coding practices, including unsynthesizable code, unintentional latches, undriven signals, race conditions, out-of-range indexing, incomplete case statements and simulation and synthesis mismatches. Verific’s parser platforms serve as the front end. It supports both ASIC and FPGA design flows.

Mixel debuted MIPI D-PHY IP compliant to the MIPI D-PHY v2.5 specification. It supports MIPI Camera Serial Interface 2 (CSI-2), as well as Display Serial Interface (DSI) and DSI-2. It also supports speeds up to 4.5Gbps per lane, an aggregate data rate of 18Gbps, and all v2.5 features not available in previous versions of the specifications. Other features include new power saving functionality such as HS-TX half swing mode and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround.

Uhnder included Moortec’s complete embedded monitoring subsystem solution in its new automotive radar-on-chip (RoC). The RoC provides high contrast resolution (HCR) technology for improved range and angular resolution as well as separation of small objects from large. Uhnder cited the Moortec’s sensing fabric as both enabling high-performance goals and meeting automotive-grade reliability.

AWS used Arm’s Neoverse N1 platform as the base for its new Graviton2 processors, which will power its general purpose (M), compute optimized (C), and memory optimized (R) portfolios. The M6g instance was noted for 40% better price performance over competitors and is available now for testing.

Synopsys reported fourth quarter and full year financial results. For Q4 2019, revenue was $851.1 million, up 7% compared to the same quarter last year. On a GAAP basis, revenue was $1.04 per share, down 37% from $1.66 per share in Q4 2018. Non-GAAP revenue per share in Q4 2019 was $1.15 per share, up 47% from $0.78 per share for the same quarter last year.

For the full year, revenue was $3.361 billion, up 7.7% compared to 2018. On a GAAP basis, $3.45 per share, up 22% from $2.82 per share in 2018. Non-GAAP revenue for the year was $4.56 per share, up 17% from $3.91 per share in 2018. The company’s software security and quality segment made up 10% of revenue this year, with EDA/IP/semiconductor services providing the rest. Synopsys expects revenue of $3.6 billion to $3.65 billion next year.

Check out upcoming industry events and conferences: The RISC-V Summit will include talks, an expo, and tutorials on the open ISA Dec. 10-12 in San Jose, CA. Next year, DesignCon will take place January 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design.

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