tag: Movellus

Week In Review: Design, Low Power
By Jesse Allen - 23 Apr, 2021 - Comments: 0

Skyworks Solutions will acquire Silicon Labs' Infrastructure & Automotive (I&A) business for $2.75 billion cash. The transaction includes Silicon Labs' power/isolation, timing and broadcast products, intellectual property, and approximately 350 employees. Silicon Labs said it will focus on its IoT business, which includes integrated hardware and software wireless platforms for multiple ... » read more

Interconnects In A Domain-Specific World
By Brian Bailey - 08 Apr, 2021 - Comments: 0

Moving data around is probably the least interesting aspect of system design, but it is one of three legs that defines the key performance indicators (KPI) for a system. Computation, memory, and interconnect all need to be balanced. Otherwise, resources are wasted and performance is lost. The problem is that the interconnect is rarely seen as a contributor to system functionality. It is seen... » read more

Integrity Problems For Edge Devices
By Brian Bailey - 14 Sep, 2020 - Comments: 0

Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices. Noise can come in... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Low-Power Analog
By Brian Bailey - 14 May, 2020 - Comments: 3

Analog circuitry is usually a small part of a large SoC, but it does not scale in the same way as digital circuitry under Moore's Law. The power consumed by analog is becoming an increasing concern, especially for battery-operated devices. At the same time, little automation is available to help analog designers reduce consumption. "Newer consumer devices, like smartphones and wearables, alo... » read more

Big Design, IP and End Market Shifts In 2020
By Brian Bailey - 30 Jan, 2020 - Comments: 0

EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

A New Dawn For IP
By Brian Bailey - 12 Dec, 2019 - Comments: 0

The IP industry is changing again. The concept started as build once, use everywhere, but today it is more like architect once, customize everywhere. Few designs can afford sub-optimal IP for their application. The need for customized IP is driven by both leading-edge designs and the trailing markets, although for different reasons. While this customization is causing IP companies to transfo... » read more

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Apr, 2019 - Comments: 0

Tools & IP Cadence entered the system design and analysis market with the release of Clarity 3D Solver, which creates S-parameter models for use in signal integrity, power integrity, and electromagnetic compliance analysis. The tool uses a distributed adaptive meshing approach for cloud and on-premises distributed computing and it optimized to distribute a job across multiple low-cost comp... » read more

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