Week In Review: Design, Low Power

Circuit simulation speedup; DSP IP for embedded vision; edge AI startup; clock distribution; Skyworks buys Silicon Labs’ infrastructure, auto biz.


Skyworks Solutions will acquire Silicon Labs’ Infrastructure & Automotive (I&A) business for $2.75 billion cash. The transaction includes Silicon Labs’ power/isolation, timing and broadcast products, intellectual property, and approximately 350 employees. Silicon Labs said it will focus on its IoT business, which includes integrated hardware and software wireless platforms for multiple protocols.

Skyworks develops analog semiconductors for wireless networking across a broad range of markets. “This acquisition will broadly expand our capabilities across high-growth end markets including automotive, communications and industrial, creating new and highly compelling opportunities for Skyworks,” said Liam K. Griffin, president and CEO of Skyworks.

Marvell Technology completed its acquisition of Inphi Corporation. The deal, worth about $10 billion in cash and stock, adds Inphi’s electro-optical networking, analog, and DSP chips to Marvell’s existing networking and data center portfolio. Matt Murphy, president and CEO of Marvell, explained the impact of the acquisition: “Inphi’s technologies are at the heart of cloud data center networks and they continue to extend their leadership with innovative new products, including 400G data center interconnect optical modules, which leverage their unique silicon photonics and DSP technologies. We believe that Inphi’s growing presence with cloud customers will also lead to additional opportunities for Marvell’s DPU and ASIC products.” Founded in 2000, Inphi was based in Santa Clara, Calif. As part of the transaction, the combined companies will be domiciled in Delaware.

Synopsys unveiled PrimeSim Continuum, a unified workflow for circuit simulation technologies. Built on next-generation SPICE and FastSPICE architectures, it utilizes GPU acceleration to speed creation of analog, RF, mixed-signal, custom digital, and memory designs. It also includes PrimeWave for a consistent and flexible environment across all engines, optimizing design set-up, analysis, and post-processing. Kioxia and Samsung Electronics are using the tool, with Samsung Electronics noting a 10X speed up with golden SPICE accuracy using heterogeneous compute acceleration on a recent 56Gbit Ethernet design.

Synopsys also introduced PrimeLib, a characterization and validation solution to produce signoff quality libraries targeted for SoC design at advanced process nodes. It is integrated with PrimeSim simulation technology, PrimeTime signoff STA validation, and includes SmartScaling for multi-PVT characterization, machine learning, and integrated validation technologies.

Movellus debuted the Maestro Intelligent Clock Network platform to orchestrate clock distribution in SoC designs. The platform combines a clock architecture, software automation, and application-optimized IP to solve common clock distribution challenges while scaling to high-performance multi- GHz frequencies in a small footprint. Along with clock generation, skew compensation, and peak power and voltage noise reduction, it features a virtual mesh to enable automatic self-regulation of clocking throughout the SoC.

sureCore released a configurable register file compiler that seeks to increase dynamic power savings and supports multiple read and write ports and is compatible with process nodes ranging from 40nm to advanced finFET. The Register File Compiler implements an architecture that supports operation down to near threshold voltages and provides seamless interconnectivity with system logic. The company said recent production projects have delivered multi-port solutions operating down to 0.45V on a 16nm process, while high speed operation can be tuned to frequencies up to 2Ghz by selecting different optimization criteria.

Siemens’ Aprisa place-and-route solution was certified for TSMC’s advanced N6 process. Aprisa tools offer complete gate-level-to-GDSII hierarchical and block level physical implementation solutions.

Cadence’s Pegasus Verification System was certified for Samsung Foundry’s 5nm and 7nm process technologies with an optimized physical verification flow. Samsung Foundry also provided an enhanced, signoff-accurate process design kit to facilitate adoption.

Cadence added two new DSP IP cores for embedded vision and AI to its Tensilica Vision DSP product family. The Tensilica Vision Q8 DSP is a 1024-bit SIMD with 3.8 TOPS for 2X performance and memory bandwidth compared to the previous generation, targeting high-end vision and imaging applications in the automotive and mobile markets. The Tensilica Vision P1 DSP is a 128-bit SIMD with 400 GOPS and is optimized for always-on and smart sensor applications in the consumer market. Both DSPs feature an N-way programming model that preserves software compatibility for an easy migration from prior-generation Tensilica Vision DSPs with different SIMD widths. They support Tensilica Instruction Extension (TIE) language, as well as XNNC and NNAPI for neural networks. Xvisio Technology and Eyeris plan to use the DSPs.

Expedera launched from stealth with an energy-efficient AI inference IP for edge systems. The Origin deep-learning accelerator provides up to 18 TOPS/W at 7nm and is focused on neural network models such as object detection, recognition, segmentation, super-resolution, and natural language processing for mobile, consumer, industrial, and automotive markets. Da Chuang, CEO and co-founder of Expedera, credits the team’s background in network processing to its approach to developing an AI accelerator. “We’ve created an AI architecture that allows us to load the entire network model as metadata and run it natively using very little memory,” Chuang said. “As our hardware processes the model monolithically, we are not constrained by memory bandwidth and can scale up to over 100 TOPS.” The startup is based in Santa Clara, Calif.

Rambus announced its HBM2E memory interface subsystem, consisting of a fully-integrated PHY and controller, has been silicon proven on Samsung Foundry’s advanced 14/11nm FinFET process. It operates up to 3.2 Gbps and delivers 410 GB/s of bandwidth for accelerators targeting AI/ML training and HPC applications.

Codasip announced two FPGA Evaluation Platforms for accelerated evaluation of Codasip RISC-V IP. The platforms are designed to target Digilent boards based on Xilinx Artix-7 and Kintex-7 FPGAs. The evaluation platforms contain the selected RISC-V processor IP core with a subsystem containing peripherals and AMBA interconnect. A testbench layer includes a clock generator and block RAMs for internal memories and can use some of the FPGA peripherals such as flash memory. Additionally included is a Vivado project and bitmap files for the target FPGA board.

Xilinx debuted the Kria portfolio of adaptive system-on-modules (SOMs), which are production-ready small form factor embedded boards aimed at rapid deployment in edge-based applications. The first product in the lineup, the K26 SOM, targets vision AI applications in smart cities and smart factories. It includes a complete software stack and pre-built accelerated applications. A full range of products is planned.

PLDA launched a line of PCIe Controller IP products tailored for use in USB4 ICs. It includes the XpressSWITCH for USB4 to implement the PCIe switch logic required in USB4 Hubs, featuring embedded multi-port switch with PIPE-attached internal endpoints, in-the-flow processing, and low power features. PCIe Controller and AXI PCIe Controller for USB4 are also available.

Rambus joined the DARPA Toolbox initiative, making all Rambus security, memory interface, and SerDes interface IP products available to DARPA researchers. The program provides access to commercial vendors’ technologies and tools via pre-negotiated, low-cost, non-production access frameworks and simplified legal terms.

Ansys is promoting data centers powered by 3rd Gen AMD EPYC processors as a way to improve simulation speed, with a recent demonstration by AMD finding that its new EPYC 75F3 processors could reduce specific Ansys simulation runtimes by up to a factor of two.

Van Oord is using Ansys Mechanical and Cloud products from Infinite Simulation Systems in the design of its next-gen offshore wind turbines. Van Oord used the tools to run more design iterations to predict the performance of advanced wind turbine foundations and enhance the fabrication processes while reducing project risks and speeding supply chain negotiations.

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The Linley Spring Processor Conference 2021 will hold its final day today, April 23. The IEEE Custom Integrated Circuits Conference (CICC 2021) will close out the month on April 25-30.

Next month will start with Women in Semiconductors on May 3. Infineon’s Virtual Power Conference will take place May 4-6, followed by the 29th IEEE International Symposium On Field-Programmable Custom Computing Machines on May 9-12. The 2021 ESD Alliance CEO Outlook will take place May 18. The 2021 Embedded Vision Summit will be held May 25-28.

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