tag: multi patterning

Tech Talk: FD-SOI vs. FinFET
By Ed Sperling - 15 Dec, 2016 - Comments: 0

Jamie Schaeffer, 22FDX program director at GlobalFoundries, talks about the future of FD-SOI, what the tradeoffs are in performance, power and cost compared with finFETs, how many mask layers and patterning steps are required for each, and when 12nm FD-SOI will be introduced. Related Stories To 7nm And Beyond GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economi... » read more

Multi-Patterning Issues At 7nm, 5nm
By Ed Sperling - 28 Nov, 2016 - Comments: 13

Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

Can We Measure Next-Gen FinFETs?
By Mark LaPedus - 21 Nov, 2016 - Comments: 6

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

More EUV Mask Gaps
By Mark LaPedus - 17 Nov, 2016 - Comments: 12

Extreme ultraviolet (EUV) lithography is at a critical juncture. After several delays and glitches, [gettech id="31045" comment="EUV"] is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again. First, the EUV source must generate more ... » read more

Mastering The Magic Of Multi-Patterning
By Mentor, a Siemens Business - 17 Nov, 2016 - Comments: 0

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on y... » read more

Why EUV Is So Difficult
By Mark LaPedus - 17 Nov, 2016 - Comments: 23

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. More recently, though, [gettech id="31045" comment="EUV"] lithography appears to be inching closer to pos... » read more

10nm FinFET Market Heats Up
By Mark LaPedus - 16 Oct, 2016 - Comments: 1

The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016. Now, Samsung Electronics said that it has commenced mass... » read more

The Pitfalls Of Auto-Stitching In Double-Patterning
By David Abercrombie - 22 Sep, 2016 - Comments: 0

Ever since the first double-pattern (DP) odd-cycle error ring was produced on a layout, designers have longed for a magic solution to solve it. Traditionally, the first approach to fixing an odd-cycle error was to move a polygon or a polygon edge to increase spacing to an adjoining polygon in the cycle. Alternatively, you could remove a polygon altogether, or split it into two pieces. All of th... » read more

Re-Coloring ECO Changes With Calibre Multi-Patterning
By Mentor, a Siemens Business - 21 Sep, 2016 - Comments: 0

Engineering change orders (ECOs) can wreak havoc on multi-patterning (MP) coloring (and time to market) if not dealt with quickly and efficiently. Design teams working on MP designs need a complete ECO enablement solution, before recoloring issues consume resources and destroy schedules. The Calibre Multi-Patterning tool provides smart, automated support for recoloring designs after ECO impleme... » read more

Introduction To Multi-Patterning
By Mentor, a Siemens Business - 20 Jul, 2016 - Comments: 0

Multi-patterning enables accurate lithographic resolution at today's most advanced nodes. Learn about the basics of this technology, and how it impacts your IC design and verification tasks and responsibilities. To read more, click here. » read more

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