tag: network on chip

Top 5 Reasons Engineers Need A Smart NoC
By Rick Bye - 27 Feb, 2025 - Comments: 0

As system-on-chip (SoC) designs grow more complex, IP interconnect engineers struggle with achieving optimal scalability, performance, and power efficiency. The increasing number of IP blocks, often ranging from 50 to more than 500, introduces significant interconnect congestion, timing closure issues, and power dissipation challenges. Additionally, many network-on-chip (NoC) design tasks are s... » read more

Boost SoC Efficiency And Speed With FlexGen Smart NoC IP Automation
By Arteris - 26 Feb, 2025 - Comments: 0

Today’s high-end SoCs contain many heterogeneous processing elements to address the needs of HPC and AI applications. These include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Tensor Processing Units (TPUs), and other hardware accelerators. Furthermore, IPs may contain clusters of these processor cores, and SoC subsystems may include arra... » read more

From DIY To Advanced NoC Solutions: The Future Of MCU Design
By Andy Nightingale - 30 Jan, 2025 - Comments: 0

The evolution of microcontrollers (MCUs) has significantly transformed embedded systems, shifting from simple, standalone processors to complex, multifunctional units that rival traditional systems-on-chip (SoCs). These advancements are fueled by the demand for increased computational efficiency, cutting-edge features like AI and machine learning (ML) integration, and the need to address growin... » read more

2024 Set The Stage For NoC Interconnect Innovations In SoC Design
By Andy Nightingale - 19 Dec, 2024 - Comments: 0

What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. A game-changing new technology was unveiled, a major product was launched, and existing solutions were tailored for AI, automotive, high-performance computing (HPC) and more. Along the way, we welcomed new partners and ... » read more

Scaling AI Chip Design With NoC Soft Tiling
By Andy Nightingale - 26 Nov, 2024 - Comments: 0

Tiling is about repeating modular units within the same chip to enhance scalability and efficiency; chiplets involve combining different silicon pieces to achieve a more diverse and powerful system within a single package. Network-on-chip (NoC) soft tiling is complimentary but distinct from chiplets described above as it repeats modular units inside a NoC design. Soft tiling within a NoC off... » read more

Scaling Performance In AI Systems
By Ed Sperling - 11 Nov, 2024 - Comments: 0

Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

Reducing SoC Power With NoCs And Caches
By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Chiplets Make Progress Using Interconnects As Glue
By Ann Mutschler - 31 Oct, 2024 - Comments: 0

Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

Accelerate AI SoC Designs with NoC Tiling
By Arteris - 30 Oct, 2024 - Comments: 0

Network-on-chip (NoC) tiling technology is revolutionizing AI and machine learning-enabled semiconductor designs. This emerging approach uses proven, robust network-on-chipIP to facilitate scaling, condense design time, speed testing and reduce design risk. It allowsSoC architects to create modular, scalable designs by replicating soft tiles across the chip. Each soft tile represents a self-con... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

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