tag: network on chip

Data Security Challenges In Automotive
By Ann Mutschler - 03 Feb, 2022 - Comments: 1

Automakers are scrambling to prevent security breaches and data hacks in new vehicles while simultaneously adding new and increasingly autonomous features into vehicles that can open the door to new vulnerabilities. These two goals are often at odds. As with security in any complex system, nothing is ever completely secure. But even getting a handle on this multilayered issue is a challenge.... » read more

Adaptive Scheduling for Time-Triggered Network-on-Chip-Based Multi-Core Architecture Using Genetic Algorithm
By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract "Adaptation in time-triggered systems can be motivated by energy efficiency, fault recovery, and changing environmental conditions. Adaptation in time-triggered systems is achieved by preserving temporal predictability through metascheduling techniques. Nevertheless, utilising existing metascheduling schemes for time-triggered network-on-chip architectures poses design time computatio... » read more

End-To-End Traceability
By Ed Sperling - 29 Nov, 2021 - Comments: 0

Despite standards such as ISO 26262 and IEC 61508, there are still disconnects and gaps in the supply chain and design-through-manufacturing flows. Kurt Shuler, vice president of marketing at Arteris IP, digs into what's missing, why changes made in one area are not reflected in other areas and throughout the product lifecycle, and why various different phases of the flow don't always match up ... » read more

What Is An xPU?
By Brian Bailey - 11 Nov, 2021 - Comments: 0

Almost every day there is an announcement about a new processor architecture, and it is given a three-letter acronym — TPU, IPU, NPU. But what really distinguishes them? Are there really that many unique processor architectures, or is something else happening? In 2018, John L. Hennessy and David A. Patterson delivered the Turing lecture entitled, "A New Golden Age for Computer Architecture... » read more

More NoC Wisdom
By Kurt Shuler - 07 Oct, 2021 - Comments: 0

A common experience for anyone promoting a disruptive technology is that prospective customers understand that what is being offered is different. Still, without a familiar reference to compare, they extrapolate expectations unreliably. Sometimes expectations are extrapolated to infinity: “My existing solution has limitations, but the new technology should have no limitations.” Sometimes ex... » read more

Using Machine Learning For Characterizations Of NoC Components
By Arteris - 06 Oct, 2021 - Comments: 0

Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of... » read more

NoC Experiences From The Trenches
By Kurt Shuler - 28 Sep, 2021 - Comments: 0

Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

Better Optimization For Many-Core AI Chips
By Richard Oxland - 10 Aug, 2021 - Comments: 0

The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

Automotive AI Hardware: A New Breed
By Kurt Shuler - 03 Jun, 2021 - Comments: 0

Arteris IP functional safety manager Stefano Lorenzini recently presented “Automotive Systems-on-Chip (SoCs) with AI/ML and Functional Safety” at the Linley Processor Conference. A main point of the presentation was that conventional wisdom on AI hardware markets is binary. There’s AI in the cloud: Big, power-hungry, general-purpose. And there’s AI at the edge: Small, low power, limited... » read more

Interconnects In A Domain-Specific World
By Brian Bailey - 08 Apr, 2021 - Comments: 0

Moving data around is probably the least interesting aspect of system design, but it is one of three legs that defines the key performance indicators (KPI) for a system. Computation, memory, and interconnect all need to be balanced. Otherwise, resources are wasted and performance is lost. The problem is that the interconnect is rarely seen as a contributor to system functionality. It is seen... » read more

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