TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms


New technical paper titled “AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors” from researchers at Technische Universitaet Dresden (TU Dresden).

Partial Abstract:
“In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability.” Published April 2022.

Find the technical paper here.

A. Kamaleldin and D. Göhringer, “AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors,” in IEEE Access, vol. 10, pp. 43895-43913, 2022, doi: 10.1109/ACCESS.2022.3168686.

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