tag: NoC

What Is Functional Accuracy?
By Ann Mutschler - 26 Mar, 2015 - Comments: 0

What it means to be functionally accurate in the context of [getkc id="104" kc_name="virtual platforms"] varies greatly, depending upon whom you ask and even when you ask them. But that doesn’t mean that functional accuracy isn’t useful. Jon McDonald, technical marketing engineer for the design and creation business at [getentity id="22017" e_name="Mentor Graphics"], expects to see a lot... » read more

NoC Reliability: Simplified
By Randy Smith - 26 Mar, 2015 - Comments: 0

Recently, the reliability features of on-chip network (NoC) IP have received much attention. One reason for this focus has been the rush of companies to get into the automotive electronics market and the explosion of new automotive features being implemented in electronic systems. While the details may vary, the high-level view of on-chip network reliability is really quite simple. At the ar... » read more

Focus More Attention On The SoC’s Central Nervous System
By Kurt Shuler - 26 Mar, 2015 - Comments: 0

In multiple conversations over the years, I’ve often compared the interconnect fabric within SoC designs to the central nervous system of the human body. The point that I try to make is that the potential of the SoC’s performance and functionality is tied to the information that travels through the fabric and interconnect to all the on-chip IP components. Improving a chip’s ability to com... » read more

Streamlining Interconnect Integration Accelerates Globally Distributed Design
By Kurt Shuler - 26 Feb, 2015 - Comments: 0

As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the compan... » read more

Tech Talk: SW vs. HW
By Ed Sperling - 21 Oct, 2014 - Comments: 0

Arteris CTO Craig Forest talks about what gets done in hardware, what gets done in software, and where the two worlds meet and sometimes collide. [youtube vid=-EbUTZL0uz8] » read more

The Week In Review: Design
By Ed Sperling - 03 Oct, 2014 - Comments: 0

IP ARM introduced a new software platform and a free operating system aimed at IoT development. The OS incorporates security, communication and device management features for improved energy efficiency. The device server simplifies the connection and management of devices, incorporating security and improving efficiency. Cadence rolled out a broad IP portfolio for TSMC's 16nm platform, and ... » read more

NoC Technology: Saving the Planet, One Chip at a Time
By Kurt Shuler - 21 Aug, 2014 - Comments: 0

In Silicon Valley, the cliché is that we are using technology to change the world in some meaningful way. However, I made some calculations recently and I found network-on-chip technology is actually contributing to efforts to reduce carbon emissions. SoC designers have become the ultimate energy misers as they strive to make tradeoffs between extending battery life and providing game-chang... » read more

Locking Down The Chip
By Ernest Worthman - 09 Jul, 2014 - Comments: 0

The push toward securing chips is complicated by the amount of third-party IP that is being used inside of today’s complex SoCs. This has cast new light on the potential for on-chip networks to also function in securing signals that flow through those networks. This becomes particularly important with the Internet of Things, because the source of those signals isn’t always obvious to the... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

Week In Review: System-Level Design
By Ed Sperling - 17 Jan, 2014 - Comments: 0

Cadence rolled out a new version of its functional verification platform, greatly improving performance and updating it to deal with the big increases in third-party and re-used IP in designs. For IP and block verification, the company said it increased formal analysis performance by up to 20% and simulation by up to 10 times. The debugger also reduces the database size by 10 times and the time... » read more

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