Scaling Performance In AI Systems

By Ed Sperling - 11 Nov, 2024 - Comments: 0

Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

NoCs In 3D Space

By Brian Bailey - 03 Apr, 2024 - Comments: 0

A network on chip (NoC) has become an essential piece of technology that enables the complexity of chips to keep growing, but when designs go 3D, or when third-party chiplets become pervasive, it's not clear how NoCs will evolve or what the impact will be on chiplet architectures. A NoC enables data to move between heterogeneous computing elements, while at the same time minimizing the resou... » read more

Optimizing IC Designs For Real-World Use Cases

By Brian Bailey - 24 Aug, 2023 - Comments: 0

Semiconductor systems are becoming more focused on power, performance, and area for the primary scenarios they are likely to see in real-world applications, but increasingly at the expense of secondary tasks. This is happening at all levels of abstraction and all stages of the design flow. At the highest level, processors are being optimized to run a given set of software. RISC-V is one of t... » read more

Not All There: Heterogeneous Multiprocessor Design Tools

By Brian Bailey - 26 Jun, 2023 - Comments: 0

The design, implementation, and programming of multicore heterogeneous systems is becoming more common, often driven by the software workloads, but the tooling to help optimize the processors, interconnect, and memory are disjointed. Over the past few years, many tools have emerged that help with the definition and implementation of a single processor, optimized for a given set of software. ... » read more

Auto Cyberattacks Becoming More Widespread

By John Koon - 02 Mar, 2023 - Comments: 0

As vehicles become smarter, more complex, and increasingly connected, they also become more prone to cyberattacks. The challenge now is to keep pace with hackers, who are continually devising new and innovative ways to attack both software and hardware in vehicles. Recent statistics bear this out. In 2022, there was a big spike in deep/dark web activity and incidents related to application p... » read more

Fast and Flexible FPGA-based NoC Hybrid Emulation

By Technical Paper Link - 14 Jul, 2022 - Comments: 0

Researchers from RWTH Aachen University and Otto-von-Guericke Universitat Magdeburg have published a new technical paper titled "EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs." Abstract: "Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling co... » read more

AI-Based Method to Prune the Design Space of Heterogeneous NoCs

By Technical Paper Link - 02 May, 2022 - Comments: 0

Abstract "Often suffering from under-optimization, Networks-on-Chip (NoCs) heavily impact the efficiency of domain-specific Systems-on-Chip. To cope with this issue, heterogeneous NoCs are promising alternatives. Nevertheless, the design of optimized NoCs satisfying multiple performance objectives is extremely challenging and requires significant expertise. Prior works failed to combine many... » read more

Who Owns A Car’s Chip Architecture

By Ed Sperling - 05 May, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, examines the competitive battle brewing between OEMs and Tier 1s over who owns the architecture of the electronic systems and the underlying chip hardware. This has become a growing point of contention as both struggle for differentiation in a market where increasingly autonomous vehicles will all behave the same way. That, in turn, has si... » read more

Applying Machine Learning

By Ann Mutschler - 13 Aug, 2017 - Comments: 0

Sundari Mitra, co-founder and CEO of NetSpeed Systems, sat down with Semiconductor Engineering to discuss machine learning, training algorithms, what customers are struggling with today, and how startups fare in an increasingly consolidated semiconductor industry. What follows are excerpts of that conversation. SE: Machine learning is booming. How will this change design? Mitra: This is a... » read more

OSDN – On-chip Software Defined Network

By Rajesh Ramanujam - 27 Oct, 2016 - Comments: 0

You must be mumbling to yourself, “Oh no, not another NoC article! The term NoC is used so loosely in the industry and everybody seem to be claiming they have one, so what more is there to say?” Fair enough, but please indulge me. Actually, there are some wannabe NoCs out there, but very few actually provide a full-fledged network. I submit, a real NoC should implement all the same key d... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?