Manufacturing Bits: Oct. 23


3D stacked finFETs At the upcoming 2018 IEEE International Electron Devices Meeting (IEDM), Imec is expected to present a paper on a 3D stacked finFET architecture. IEDM is slated from Dec. 1-5 in San Francisco. Imec’s technology is based what on the R&D organization calls sequential integration. Another R&D organization, Leti, calls it 3D monolithic integration. Regardless, the idea... » read more

TFETs Cut Sub-Threshold Swing


One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

Pathfinding Beyond FinFETs


Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

System Bits: July 9


New quantum computing algorithm Researchers at the University of California, San Diego, have proposed a new algorithm for quantum computing that they believe will speed a particular type of problem…but swifter calculations would come at the cost of greater physical resources devoted to precise timekeeping. The algorithm would be used to conduct a task called an unstructured search. The go... » read more