tag: NXP

Matter Security And Privacy Fundamentals
By Infineon - 03 Aug, 2022 - Comments: 0

As the Internet of things (IoT) connects more devices and systems, cyberattacks increase. This situation drives concern and hesitation by users and limiting adoption. To address these obstacles, Matter was created with security and privacy as key design tenets. This CSA whitepaper walks through: Security concepts for the smart home Smart home cybersecurity challenges and risks Matter... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 29 Jul, 2022 - Comments: 1

The U.S. Congress approved the CHIPS Act, a mammoth bipartisan achievement the New York Times called “the most significant government intervention in industrial policy in decades.” As passed, the full package — now called the Chips and Science Act — contains $52 billion in direct assistance for the semiconductor industry, along with $24 billion in tax incentives. In addition, the bill c... » read more

Week in Review: Auto, Security, Pervasive Computing
By Marie C. Baca - 08 Jul, 2022 - Comments: 0

Automotive The European Union plans to approve sales of fully autonomous vehicles by the end of September, according to Politico. The legislative package will allow for the registration and sale of up to 1,500 vehicles per model per year in member countries. Level 4 autonomous vehicles are still in the development stage, but reducing human error in autos is a crucial part of the EU’s goal to... » read more

Blog Review: July 6
By Jesse Allen - 06 Jul, 2022 - Comments: 0

Synopsys' Mike Gianfagna looks at how the data center paradigm has shifted in the last ten years with an exponential increase in the amount of data demanding new approaches to storage that rely on distributed networks. Cadence's Frank Schirrmeister explains multidisciplinary design analysis and optimization, or MDAO, and how it is being combined with machine learning models to enhance classi... » read more

Week In Review: Manufacturing, Test
By Ed Sperling - 17 Jun, 2022 - Comments: 0

Node scaling wars are revving up, although much of the action is happening where most people can't see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can't keep. Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDM... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Jun, 2022 - Comments: 0

Tools, design, chips Altair, a provider of software and cloud services for CAE, HPC, simulation, and data analysis, acquired Concept Engineering, a provider of automatic schematic generation tools, electronic circuit and wire harness visualization platforms that provide on-the-fly visual rendering, and electronic design debug solutions. “Concept Engineering’s advanced, reactive visualizati... » read more

Blog Review: May 18
By Jesse Allen - 18 May, 2022 - Comments: 0

Coventor's Gerold Schropfer considers taking an approach from the early days of computing and using MEMS technology to create computers based on micro-scale electro-mechanical logic and memory for emerging low-energy computing applications such as autonomous sensor nodes and edge computing. Synopsys' Morten Christiansen explains how USB4 differs from USB 3.2, allowing simultaneous host-to-ho... » read more

Auto Chipmakers Dig Down To 10ppb
By Anne Meixner - 08 Mar, 2022 - Comments: 0

How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them. Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, ... » read more

Blog Review: Feb. 9
By Jesse Allen - 09 Feb, 2022 - Comments: 0

Arm's Mark Inskip walks through how the Morello program built a demonstration of the architecture that enables fine-grained memory protection and highly scalable software compartmentalization based on the CHERI (Capability Hardware Enhanced RISC Instructions) architectural model, from IP development and SoC design to creating software and a demonstration board. Synopsys' Plamen Asenov and su... » read more

Blog Review: Jan. 19
By Jesse Allen - 19 Jan, 2022 - Comments: 0

Synopsys' Anand Thiruvengadam examines the memory chip design challenges of optimizing PPA, speeding turnaround time, and improving reliability and how a shift-left approach can help. Cadence's Paul McLellan checks out some of TSMC's recent updates in 3D packaging and the importance of thermal analysis and finding the right balance between IR-drop and TSV usage in multi-chip physical verific... » read more

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