Blog Review: Oct. 5

Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

Blog Review: Sept. 24

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

The Week In Review: Design

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more