Partitioning In The Chiplet Era


The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs. Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be short... » read more

Top 5 Reasons The SoC Interconnect Matters


The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

Advanced SoC Interconnect IP


By Kurt Shuler I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year. But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward. The one lesson learned is that flexibility for SoC designs is increasingly more important. In ... » read more

Chip Economics


The concise research paper, "NoC Interconnect Improves SoC Economics: Initial Investment is Low Compared to SoC Performance and Cost Benefits," by Objective Analysis Semiconductor Market Research, provides quantitative data from user experiences comparing the costs and benefits of implementing network on chip SoC interconnects versus traditional bus and crossbar interconnects. You will learn... » read more