Heterogeneous Computing Raises The Bar For Functional Verification

By Raik Brinkmann - 29 Nov, 2018 - Comments: 0

If there’s one thing certain in chip development, it’s that every innovation in architecture or semiconductor technology puts more pressure on the functional verification process. The increase in gate count for each new technology node stresses tool capacity. Every step up in complexity makes it harder to find deep, corner-case bugs. The dramatic growth in SoC designs brings software into p... » read more

Bare Metal Programming

By Ann Mutschler - 29 Nov, 2018 - Comments: 0

As the need for safety and security grows across application areas such as automotive, industrial, and in the cloud, the semiconductor industry is searching for the best ways to protect these systems. The big question is whether it is better to build security and safety into hardware, into software, or both. The answer isn't entirely clear yet, but one of the options under consideration is s... » read more

Heterogeneous Computing Verification

By Ed Sperling - 28 Nov, 2018 - Comments: 0

Raik Brinkmann, CEO of OneSpin Solutions, looks at new architectures involving AI and machine learning, what changes in these multi-accelerator, multi-memories designs, and where problems can crop up both in design and verification. https://youtu.be/0Trtfq8_hKg See other tech talk videos here. » read more

The Impact of Domain Crossing on Safety

By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

The Impact of Moore’s Law Ending

By Brian Bailey - 29 Oct, 2018 - Comments: 2

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 26 Oct, 2018 - Comments: 0

Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

Integrating Results And Coverage From Simulation And Formal

By Tom Anderson - 25 Oct, 2018 - Comments: 0

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

EDA Cloud Adoption Hits Speed Bumps

By Brian Bailey - 25 Oct, 2018 - Comments: 0

If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is cer... » read more

RISC-V: More Than a Core

By Brian Bailey - 15 Oct, 2018 - Comments: 2

The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V's success. The real value that RISC-V brings is the promise of an ecosystem and the opportun... » read more

Adding Safety Into Automotive Design

By Ann Mutschler - 04 Oct, 2018 - Comments: 0

The ISO 26262 spec is a household term for anyone even remotely involved with the automotive industry today. Increasingly, though, it is being used interchangeably with safety-readiness across the entire supply chain. ISO 26262 compliance is a prerequisite for IP and chips used in an increasing number of automotive applications. It applies to systems, software, and to individual products. An... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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