How to verify increasingly complex chips.
Raik Brinkmann, CEO of OneSpin Solutions, looks at new architectures involving AI and machine learning, what changes in these multi-accelerator, multi-memories designs, and where problems can crop up both in design and verification.
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Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.
Why this is becoming a bigger issue, and what can be done to mitigate the effects.
Some 300mm tools are converted to 200mm; equipment prices and chip manufacturing costs are rising.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.
Disaggregation and the wind-down of Moore’s Law have changed everything.
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