How to verify increasingly complex chips.
Raik Brinkmann, CEO of OneSpin Solutions, looks at new architectures involving AI and machine learning, what changes in these multi-accelerator, multi-memories designs, and where problems can crop up both in design and verification.
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Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.
No shortage of alternatives as materials, packaging and architectural options grow, and plenty of startups are jumping in.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Semiconductor design lags behind other industries in adopting the cloud, but there could be some good reasons for that. Change is difficult.
Behind closed doors: Semiconductor executives talk about the bugs they fear the most and the problems solving them.
New data flow, higher switch density and IP integration create issues across the design flow.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
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