How to verify increasingly complex chips.
Raik Brinkmann, CEO of OneSpin Solutions, looks at new architectures involving AI and machine learning, what changes in these multi-accelerator, multi-memories designs, and where problems can crop up both in design and verification.
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Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
Researchers digging into ways around the von Neumann bottleneck.
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
Why data scrubbing and social issues could limit the speed of adoption and the usefulness of this technology.
Wally Rhines, Mentor’s CEO Emeritus, points to big shifts caused by AI, customization, uncertainty in the global economy and a changing customer base.
Smaller features and AI are creating system-level issues, but traditional ways of solving these problems don’t always work.
Agile development is gaining traction for developing hardware testbenches, but challenges remain.
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