Targeting And Tailoring eFPGAs


Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to discuss what's changing in the embedded FPGA world, why new levels of customization are so important, and difficulty levels for implementing embedded programmability. What follows are excerpts of that discussion. SE: There are numerous ways you can go about creating a chip these days, but many of the prot... » read more

Basics Of Embedded FPGA Acceleration


Making a chip run faster is no longer guaranteed by shrinking features or moving to a different manufacturing process. It now requires a fundamental change in the architecture of the chip itself. The days of the single-processor, or even single multi-core processors, are gone. The focus has shifted to different kinds of processors for different kinds of data and many different protocols and ... » read more

Cutting CapEx, Not Capacity


‘The cloud’ has been an industry buzz word for some time now, and while the initial focus was on data storage and sharing - and spawned the likes of Dropbox – ‘cloud computing’ is currently the latest trend. For instance, Amazon’s cloud platform, Amazon Web Services (AWS), gives users access to servers and a range of applications. Storage is available as before but so too now are... » read more

Using FPGAs To Accelerate Data Centers


With the technology industry at a crossroads — the effective repeal of Mooreʹs Law and the stagnation and decline of PC, tablet, consumer electronics and smartphone markets — data centers have become the sweet spot of the technology sector, showing healthy revenue growth and attracting new system solutions in both hardware and software. Unlike the ethereal promise of upcoming wonders from ... » read more

Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Towards A Metric To Measure Verification Computing Efficiency


Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

Toward Smarter Design Automation


In less than two weeks, the EDA industry will convene for its biggest conference of the year, the Design Automation Conference, again in San Francisco. Last year, I “came clean” with a post called “Confessions Of An ESL-Aholic,” pointing out that beyond high-level synthesis, a significant shift towards a more abstract design description than RTL has not yet happened and that a lot of th... » read more