Enhancing Compute Security Architecture For New-Age Applications

By Ajay Kapoor - 05 Dec, 2024 - Comments: 0

New-age AI-powered applications are becoming increasingly essential in our daily lives. Continuing to do so requires that these applications and services meet three primary challenges: Achieving high performance for complex compute tasks. Ensuring cost-effectiveness and seamless integration with existing infrastructure. Maintaining robust security and privacy measures. Historicall... » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators

By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Heterogenous Computing & Cache Attacks

By Technical Paper Link - 12 Aug, 2022 - Comments: 0

Researchers at imec-COSIC, KU Leuven presented this paper titled "Double Trouble: Combined Heterogeneous Attacks on Non-Inclusive Cache Hierarchies" at the USENIX Security Symposium in Boston in August 2022. Note, this is a prepublication paper. Abstract: "As the performance of general-purpose processors faces diminishing improvements, computing systems are increasingly equipped with domai... » read more

Audio, Visual Advances Intensify IC Design Tradeoffs

By Ann Mutschler - 13 Jun, 2022 - Comments: 0

A spike in the number of audio and visual sensors is greatly increasing design complexity in chips and systems, forcing engineers to make tradeoffs that can affect performance, power, and cost. Collectively, these sensors generate so much data that designers must consider where to process different data, how to prioritize it, and how to optimize it for specific applications. The tradeoffs in... » read more

Dynamically Reconfiguring Logic

By Ed Sperling - 12 Jul, 2021 - Comments: 0

Dynamic reconfiguration of semiconductor logic has been possible for years, but it never caught on commercially. Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, explains why this capability has been so difficult to utilize, what’s changed, how a soft logic layer can be used to control when to read, compute, steer, and write data back to memory, and ... » read more

ACAP At The Edge With The Versal AI Edge Series

By Xilinx - 30 Jun, 2021 - Comments: 0

This white paper introduces the AI Edge series to the Versal ACAP portfolio, a domain-specific architecture (DSA) that meets the strenuous demands of systems implemented in the 7nm silicon process. This series is optimized to meet the performance-per-watt requirements of edge nodes at or near the analog-digital boundary. Here, immediate response to the physical world is highly valued, and in ma... » read more

PCIe 5.0 Drill-Down

By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

Finding And Avoiding Concurrency Bugs

By Luis Murillo - 25 Apr, 2019 - Comments: 0

Understanding the intended and unintended interactions between hardware and software components is changing as architectures become more heterogeneous and interconnect topologies get more complicated. This affects performance, power consumption and cost of the project. Lots of universities are researching this from a software perspective, while a small number are looking at the implications fro... » read more

Benchmarks For The Edge

By Ed Sperling - 07 Feb, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about benchmarking in edge devices, particularly for convolutional neural networks. https://youtu.be/-beVEpKAM4M » read more

More 2.5D/3D, Fan-Out Packages Ahead

By Mark LaPedus - 15 Jan, 2019 - Comments: 0

A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year. The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advan... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: heterogeneous computing