Metrology Advances Step Up To Sub-2nm Device Node Needs


Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

CD Spec For Curvilinear Masks


Within the photomask industry, there's a major transformation from conventional Manhattan masks to more advanced curvilinear masks. Researchers from D2S and Micron Technology propose an equivalent CD spec for the curvy masks and use this spec to show that curvy masks have smaller mask variations than Manhattan masks. Find the technical paper here. Published June 2024. Linyong (Leo) Pang, ... » read more

Single Vs. Multi-Patterning Advancements For EUV


As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Navigating The GPU Revolution


Experts at the Table: Semiconductor Engineering sat down to discuss the impact of GPU acceleration on mask design and production and other process technologies, with Aki Fujimura, CEO of D2S; Youping Zhang, head of ASML Brion; Yalin Xiong, senior vice president and general manager of the BBP and reticle products division at KLA; and Kostas Adam, vice president of engineering at Synopsys. What f... » read more

193i Lithography Takes Center Stage…Again


Cutting-edge lithography to create smaller features increasingly is being supplemented by improvements in lithography for mature process nodes, both of which are required as SoCs and complex chips are decomposed and integrated into advanced packages. Until the 7nm era, the primary goal of leading-edge chipmakers was to pack everything onto a single system-on-chip (SoC) using the same process... » read more

Multi-Beam Mask Writers Are A Game Changer


The eBeam Initiative’s 11th annual Luminaries survey in 2022 reported strong purchasing predictions for multi-beam mask writers, enabling both EUV and curvilinear photomask growth. A panel of experts debated remaining barriers to curvilinear photomask adoption during an event co-located with the SPIE Photomask Technology Conference in late September. Industry luminaries representing 44 compan... » read more

Unsolved Issues In Next-Gen Photomasks


Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Photomask Challenges At 3nm And Beyond


Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Business, Technology Challenges Increase For Photomasks


Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Inverse lithography technology: 30 years from concept to practical, full-chip reality


Published in the Journal of Micro/Nanopatterning, Materials, and Metrology, Aug. 31, 2021. Read the full technical paper here (open access). Abstract In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. T... » read more

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