tag: OPC

The Process Design Kit: Protecting Design Know-How
By John Ferguson - 08 Nov, 2018 - Comments: 2

Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each company. In these days, when designs contained hundreds of transistors, companies modeled each feature in an IC at a first principles level, meaning each transistor or fundamental device was analyzed an... » read more

New Patterning Options Emerging
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

What Does An IoT Chip Look Like?
By Ed Sperling - 19 Jul, 2017 - Comments: 4

By Ed Sperling and Jeff Dorsch Internet of Things chip design sounds like a simple topic on the face of it. Look deeper, though, and it becomes clear there is no single IoT, and certainly no type of chip that will work across the ever-expanding number of applications and markets that collectively make up the IoT. Included under this umbrella term are sensors, various types of processors, ... » read more

Conflicting Goals In Data Centers
By Gale Morrison - 06 Apr, 2017 - Comments: 0

Two conflicting goals are emerging inside of data centers—speed at any cost, and the ability to extend hardware well beyond its expected lifetime to amortize that cost. Layered across both of those are concerns about how to move data back and forth more efficiently, how to secure it, and how to best integrate different generations of technology. But these widely different goals have create... » read more

Big Changes In Patterning
By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

Battling Fab Cycle Times
By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Deploying Multi-Beam Mask Writers
By Mark LaPedus - 22 Sep, 2016 - Comments: 3

Elmar Platzgummer, chief executive of IMS Nanofabrication, sat down with Semiconductor Engineering to discuss the company’s deal with Intel, photomasks, multi-beam mask writer technology and other topics. What follows are excerpts of that conversation. SE: This has been a significant year for IMS for two reasons. First, Intel recently announced plans to acquire IMS. Second, at the recent ... » read more

7nm Fab Challenges
By Mark LaPedus - 21 Apr, 2016 - Comments: 3

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

Multi-Beam Market Heats Up
By Mark LaPedus - 17 Mar, 2016 - Comments: 3

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market. In one surprising move, [getentity id="22846" e_name="Intel"] is in the process of acquiring IMS Nanofabrication, a [gettech id="31058" t_name="multi-beam e-beam"] equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer t... » read more

Taming Mask Metrology
By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

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